Analogue circuit synthesis from performance specifications

IEE Colloquium (Digest)

Volumn , Issue 331, 1997, Pages

  Lam, Yvonne ^a   Zwolinski, Mark ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; CONSTRAINT THEORY; ELECTRIC NETWORK PARAMETERS; ELECTRIC NETWORK TOPOLOGY; MATHEMATICAL MODELS; SIMULATED ANNEALING;

ANALOG CIRCUIT SYNTHESIS; GLOBAL OPTIMIZATION TECHNIQUES;

LINEAR NETWORK SYNTHESIS;

EID: 0031270447     PISSN: 09633308     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (6)

1. Degrauwe, M.G.R., Nys, O., Dijkstra, J., Bitz, S., Goffart, B.v.A.G., Vittoz, E., Cserveny, S., Meixenberger, C., Stappen, G.V.D., and Oguey, H.J. "IDAC: An iterative Design Tool for Analog Circuits". IEEE Journal of Solid-State Circuits 22(6): 1106-1115, 1987.
2. El-Turky, F. and Perry, E.E. "BLADES: An Artificial Intelligence Approach to Analog Circuit Design". IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 8(6): 680-692, 1989.
3. Harjani, R., Rutenbar, R.A., and Carley, L.R. "OASYS: A Framework for Analog Circuit Synthesis". IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 8(12): 1247-1265, 1989.
4. Gielen, G.G.E., Walscharts, H.C.C., and Sansen, W.M.C. "Analogue Circuit Design Optimisation based on Symbolic Simulation and Simulated Annealing". IEEE Journal of Solid-State Circuits 25(3):707-713, 1990.
5. Brayton, R.K., Hachtel, G.D., and Sangiovanni-Vincentelli, A.L. "A Survey of Optimisation Techniques for Integrated-Circuit Design." Proceedings of the IEEE 69(10):1334-1364, 1981.
6. Kirkpatrick, S., Gelatt, C.D., and Vecchi, M.P.J. "Optimisation by Simulated Annealing." Science 220(4598):671-680, 1983.