A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 11, 1997, Pages 1635-1648

  Gerosa, Gianfranco ^a,b,c,d,e   Alexander, Mike ^b,c,e,f,g   Alvarez, Jose ^b,e,h,i,j   Croxton, Cody ^a,b,e,k,l   D'Addeo, Michael ^b,e,m,n   Kennedy, A Richard ^b,e,o,p   Nicoletta, Carmine ^a,b   Nissen, James P ^b   Philip, Ross ^b   Reed, Paul ^b   Sanchez, Hector ^a,b   Taylor, Scott A ^b   Burgess, Brad ^a,b  

^a IEEE   (United States)

^b Somerset Design Center   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^d OHIO STATE UNIVERSITY   (United States)

^e MOTOROLA INC   (United States)

^f Semiconductor Sector ^*  (United States)

^g MOTOROLA INC   (United States)

^h TULANE UNIVERSITY   (United States)

ⁱ SOUTHERN METHODIST UNIVERSITY   (United States)

^j UNIVERSITY OF TEXAS AT ARLINGTON   (United States)

^k TEXAS A AND M UNIVERSITY   (United States)

^l National Technological University

^m NORTHEASTERN UNIVERSITY   (United States)

ⁿ HEWLETT PACKARD COMPANY   (United States)

^o UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^p UNIVERSITY OF TEXAS   (United States)

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Author keywords

Integrated L2 controller; Mobile computing; PowerPC; RISC microprocessor; Thermal assist unit

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER WORKSTATIONS; INTERFACES (COMPUTER); PERSONAL COMPUTERS; PIPELINE PROCESSING SYSTEMS; RANDOM ACCESS STORAGE; REDUCED INSTRUCTION SET COMPUTING; RESPONSE TIME (COMPUTER SYSTEMS);

INSTRUCTION CACHE THROTTLING MECHANISM; INTEGRATED L2 CONTROLLER; MOBILE COMPUTING; POWERPC MICROPROCESSOR; THERMAL ASSIST UNIT; THERMAL MANAGEMENT;

MICROPROCESSOR CHIPS;

EID: 0031270257     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.641684     Document Type: Article

References (11)

1. P. Reed et al., "A 250MHz 5W RISC microprocessor with on-chip L2 cache controller," in ISSCC Dig. Tech. Papers, Feb. 1997, pp. 412-413.
2. A. R. Kennedy et al., "A G3 PowerPC™ superscalar low-power microprocessor," in Proc. COMPCON 1997, Feb. 1997.
3. H. Sanchez et al., "Thermal management system for high performance PowerPC™ microprocessors," in Proc. COMPCON 1997, Feb. 1997.
4. G. Gerosa et al., "A 2.2W, 80MHz superscalar RISC microprocessor," IEEE J. Solid-State Circuits, vol. 29, pp. 1440-1454, Dec. 1994.
5. B. G. Burgess and S. P. Litch, "Advanced alterable pipeline timer (ADAPT): A tool to design a high performance PowerPC™ microprocessor," IPCCC, Feb. 6, 1997.
6. H. Sanchez et al., "A CMOS temperature sensor for PowerPC™ RISC microprocessors," in 1997 Symp. VLSI Circuits, June 1997, to be presented.
7. J. K. F. Lee and A. J. Smith, "Branch prediction strategies and branch target buffer design," Comput., pp. 6-22, Jan. 1984.
8. J. Alvarez et al., "A scalable resistor-less PLL design for PowerPC™ microprocessors," in ICCD '96, Oct. 7, 1996, pp. 293-300.
9. S. Voldman et al., "Analysis of snubber-clamped diode string mixed voltage interface ESD protection network for advanced microprocessors," in EOS/ESD Symp., Sept. 1995, pp. 43-61.
10. MacBench® 4.0, Ziff-Davis Benchmark Operation, Ziff-Davis Publishing Company, Morrisville, NC, 1996 (http:// www.zdnet.com/zdbop/).
11. H. Sanchez et al., "A 200MHz 2.5V superscalar RISC microprocessor," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 218-219.