A 100-MHz 4-mW four-quadrant BiCMOS analog multiplier

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 10, 1997, Pages 1568-1572

  Franciotta, M ^a   Colli, G ^b   Castello, R ^c  

^a CSEM   (Switzerland)

^b STMicroelectronics USA   (United States)

^c UNIVERSITY OF PAVIA   (Italy)

Author keywords

Analog multipliers; BiCMOS analog integrated circuits

Indexed keywords

BIPOLAR SEMICONDUCTOR DEVICES; CMOS INTEGRATED CIRCUITS; LINEAR INTEGRATED CIRCUITS; SIGNAL DISTORTION; TRANSCONDUCTANCE;

FOUR QUADRANT ANALOG MULTIPLIER; TOTAL HARMONIC DISTORTION;

MULTIPLYING CIRCUITS;

EID: 0031258327     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.634666     Document Type: Article

References (8)

1. B. Gilbert, "A precise four-quadrant multiplier with sub nanosecond response," IEEE J. Solid-State Circuits, vol. SC-3, pp. 365-373, Dec. 1968.
2. _, "A four-quadrant analog divider/multiplier with 0.01% distortion," in ISSCC Dig. Tech. Papers, 1983, pp. 248-249.
3. J. N. Babanezhad and G. C. Temes, "A 20 V four quadrant CMOS analog multiplier," IEEE J. Solid-State Circuits, vol. SC-20, pp. 1158-1168, Dec. 1985.
4. S. C. Qin and R. L. Geiger, "A ±5 V CMOS analog multiplier," IEEE J. Solid-State Circuits, vol. SC-22, pp. 1143-1146, Dec. 1987.
5. Z. Wang, "A CMOS four-quadrant analog multiplier with single ended voltage output and improved temperature performance," IEEE J. Solid-State Circuits, vol. 26, pp. 1293-1301, Sept. 1991.
6. S. L. Wang et al., "Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stage," IEEE J. Solid-State Circuits, vol. 21, pp. 1120-1122, Dec. 1986.
7. H.-J. Song and C. Kirn, "An MOS four-quadrant multiplier using simple two-input squaring circuits with source followers," IEEE J. Solid-State Circuits, vol. 25, pp. 841-847, June 1990.
8. R. Alini, A. Baschirotto, and R. Castello, "Tunable BiCMOS continuous-time filter for high-frequency applications," IEEE J. Solid-State Circuits, vol. 27, pp. 1905-1915, Dec. 1992.