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Volumn 32, Issue 10, 1997, Pages 1582-1587

An ultralow power CMOS/SIMOX programmable counter LSI

Author keywords

CMOS; Low power; Low voltage; PLL; Prescalar; SIMOX; SOI

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCY SYNTHESIZERS; PHASE LOCKED LOOPS; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY; THIN FILMS;

EID: 0031258096     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.634669     Document Type: Article
Times cited : (19)

References (11)
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  • 3
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    • Kado, Y.1    Okazaki, Y.2    Suzuki, M.3    Kobayashi, T.4
  • 6
    • 0025491670 scopus 로고
    • Practical reduction of dislocation density in SIMOX wafers
    • S. Nakashima and K. Izumi, "Practical reduction of dislocation density in SIMOX wafers," Electron. Lett., vol. 26, no. 20, pp. 1647-1649, 1990.
    • (1990) Electron. Lett. , vol.26 , Issue.20 , pp. 1647-1649
    • Nakashima, S.1    Izumi, K.2
  • 7
    • 0029357116 scopus 로고
    • Experimental 0.25-μm CMOS process with novel isolation technique for ultra-thin-film fully-depleted SIMOX devices
    • T. Ohno, Y. Kado, M. Harada, and T. Tsuchiya, "Experimental 0.25-μm CMOS process with novel isolation technique for ultra-thin-film fully-depleted SIMOX devices," IEEE Trans. Electron Devices, vol. 42, no. 8, pp. 1481-1486, 1995.
    • (1995) IEEE Trans. Electron Devices , vol.42 , Issue.8 , pp. 1481-1486
    • Ohno, T.1    Kado, Y.2    Harada, M.3    Tsuchiya, T.4
  • 8
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    • A single-chip, 1.2-GHz, PLL frequency synthesizer using reduced capacitance, dual gate, BiCMOS technology
    • K. Huehne, D. Moeller, K. Stierman, and D. Stofa, "A single-chip, 1.2-GHz, PLL frequency synthesizer using reduced capacitance, dual gate, BiCMOS technology," in Proc. CICC, 1992, pp. 24.3.1-24.3.5.
    • (1992) Proc. CICC
    • Huehne, K.1    Moeller, D.2    Stierman, K.3    Stofa, D.4
  • 9
    • 3943086463 scopus 로고
    • A high-speed & low-voltage PLL frequency synthesizer LSI using Bi-CMOS technology
    • S. Saito, H. Suzuki, T. Akiyama, K. Nonaka, T. Yamauchi, and H. Ichikawa, "A high-speed & low-voltage PLL frequency synthesizer LSI using Bi-CMOS technology," IEICE Japan Tech. Rep., vol. ICD 88-69, pp. 43-47, 1988.
    • (1988) IEICE Japan Tech. Rep. , vol.69-88 ICD , pp. 43-47
    • Saito, S.1    Suzuki, H.2    Akiyama, T.3    Nonaka, K.4    Yamauchi, T.5    Ichikawa, H.6
  • 10
    • 0027576930 scopus 로고
    • A 1-GHz/0.9-mW CMOS/SIMOX divide-by-128/129 dual-modulus prescaler using a divide-by-2/3 synchronous counter
    • Y. Kado, M. Suzuki, K. Koike, Y. Omura, and K. Izumi, "A 1-GHz/0.9-mW CMOS/SIMOX divide-by-128/129 dual-modulus prescaler using a divide-by-2/3 synchronous counter," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 513-517, 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , Issue.4 , pp. 513-517
    • Kado, Y.1    Suzuki, M.2    Koike, K.3    Omura, Y.4    Izumi, K.5
  • 11
    • 0027867597 scopus 로고
    • Enhanced performance of multi-GHz PLL LSI's using sub-1/4-micron gate ultra thin-film CMOS/SIMOX technology with synchrotron X-ray lithography
    • Y. Kado, T. Ohno, M. Harada, K. Deguchi, and T. Tsuchiya, "Enhanced performance of multi-GHz PLL LSI's using sub-1/4-micron gate ultra thin-film CMOS/SIMOX technology with synchrotron X-ray lithography," in Tech. Dig. IEEE Int. Electron Devices Meeting, 1993, pp. 243-245.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.