An efficient FPGA technology mapping tightly coupled with logic minimization

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E80-A, Issue 10, 1997, Pages 1807-1812

  Rang, Y I ^a   Ohm, Seong Yong ^a,b   Jhont, Chu Shik ^a,b  

^a Seoul National University   (South Korea)

^b Seoul Women University   (South Korea)

Author keywords

Boolean network; Field programmable gate array; Logic minimization; Logic synthesis; Technology mapping

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; GRAPH THEORY; LOGIC CIRCUITS; OPTIMIZATION;

BOOLEAN NETWORK; FIELD PROGRAMMABLE GATE ARRAY; LIBRARY MANAGEMENT TECHNIQUE; LOGIC MINIMIZATION; TECHNOLOGY MAPPING;

LOGIC DESIGN;

EID: 0031247231     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

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