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IEEE Concurrency

Volumn 5, Issue 4, 1997, Pages 18-28

  Liszka, Kathy J ^a,d,e,f   Antonio, John K ^b,f,g,h   Siegel, Howard Jay ^c,i,j  

^a UNIVERSITY OF AKRON   (United States)

^b TEXAS TECH UNIVERSITY   (United States)

^c PURDUE UNIVERSITY   (United States)

^d The University of Akron   (United States)

^e KENT STATE UNIVERSITY   (United States)

^f IEEE   (United States)

^g Department of Electrical and Computer Engineering   (United States)

^h TEXAS A AND M UNIVERSITY   (United States)

ⁱ MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^j PRINCETON UNIVERSITY   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; COST EFFECTIVENESS; FAULT TOLERANT COMPUTER SYSTEMS; GRAPH THEORY; MATHEMATICAL MODELS; MULTIPROGRAMMING; PARALLEL PROCESSING SYSTEMS;

PROGRAM TRACING;

INTERCONNECTION NETWORKS;

EID: 0031245246     PISSN: 10923063     EISSN: None     Source Type: Journal    
DOI: 10.1109/4434.641622     Document Type: Review

References (12)

1. G.B. Adams III, D.P. Agrawal, and H.J. Siegel, "A Survey and Comparison of Fault-Tolerant Multistage Interconnection Networks," Computer, June 1987, pp. 14-27.
2. D.H. Lawrie, "Access and Alignment of Data in an Array Processor," IEEE Trans. Computers, Dec. 1975, pp. 1145-1155.
3. V.E. Benes, Mathematical Theory of Connecting Networks and Telephone Traffic, Academic Press, San Diego, 1965.
4. H.J. Siegel, Interconnection Networks for Large-Scale Parallel Processing: Theory and Case Studies, 2nd ed., McGraw-Hill, New York, 1990.
5. L.W. Tucker and G.G. Robertson, "Architectures and Applications of the Connection Machine," Computer, Aug. 1988, pp. 26-38.
6. C.B. Stunkel et al., "The SP2 High-Performance Switch," IBM Systems J., Vol. 34, No. 2, 1995, pp. 185-204.
7. H.J. Siegel et al., "The Design and Prototyping of the PASM Reconfigurable Parallel Processing System," in Parallel Computing: Paradigms and Applications, A. Y. Zomaya, ed., Int'l Thomson Computer Press, London, 1996, pp. 78-114.
8. H.J. Siegel, J.B. Armstrong, and D.W. Watson, "Mapping Computer-Vision-Related Tasks onto Reconfigurable Parallel-Processing Systems," Computer, Feb. 1992, pp. 54-63.
9. S. Abraham and K. Padmanabhan, "The Twisted Cube Topology for Multiprocessors: A Study in Network Asymmetry," J. Parallel and Distributed Computing, Sept. 1991, pp. 104-110.
10. M. Malek and W. W. Myre, "Figures of Merit for Interconnection Networks," Proc. Workshop Interconnection Networks for Parallel and Distributed Processing, IEEE Press, Piscataway, N.J., 1980, pp. 74-83.
11. A.A. Chien and M. Konstantinidou, "Workloads and Performance Metrics for Evaluating Parallel Interconnects," IEEE CS Computer Architecture Technical Committee Newsletter, Summer/ Fall 1994, pp. 23-27.
12. S.H. Bokhari, "Multiphase Complete Exchange on Paragon, SP2, and CS-2," IEEE Parallel & Distributed Technology, Fall 1996, pp. 45-59.