Analysis of Metastable Operation in a CMOS Dynamic D-Latch

Analog Integrated Circuits and Signal Processing

Volumn 14, Issue 1-2, 1997, Pages 143-157

  Juan Chico, J ^a,b   Bellido, M J ^a,b   Acosta, A J ^a,b   Valencia, M ^a,b   Huertas, J L ^a,b,c,d  

^a Centro Informatico Cientifico de Andalucia   (Spain)

^b UNIVERSITY OF SEVILLE   (Spain)

^c PHILIPS HEALTHCARE   (United States)

^d INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

Author keywords

High performance CMOS VLSI design; Mean time between failures; Metastability in dynamic latches; Synchronization and arbitration

Indexed keywords

DATA STORAGE EQUIPMENT; DESIGN; FLIP FLOP CIRCUITS; MATHEMATICAL MODELS; OPERATIONS RESEARCH; PERFORMANCE; SIMULATION; SYNCHRONIZATION; VLSI CIRCUITS;

DYNAMIC LATCHES;

CMOS INTEGRATED CIRCUITS;

EID: 0031237521     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1007/978-1-4615-6101-9_12     Document Type: Article

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