Definition of effective channel length (Leff) in deep submicron mosfets based on numerically simulated surface potential

Solid-State Electronics

Volumn 41, Issue 9, 1997, Pages 1377-1382

  Niu, G F ^a,c   Chen, R M M ^a   Ruan, G ^b   Tang, T A ^b  

^a CITY UNIVERSITY OF HONG KONG   (Hong Kong)

^b FUDAN UNIVERSITY   (China)

^c AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC VARIABLES MEASUREMENT; ION IMPLANTATION; SEMICONDUCTOR JUNCTIONS; SUBSTRATES;

ARSENIC IMPLANTATION; CHANNEL RESISTANCE METHOD; CURRENT VOLTAGE EQUATION; SUBSTRATE BIAS;

MOSFET DEVICES;

EID: 0031235460     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(97)00076-2     Document Type: Article

References (9)

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6. Hu, G. J., Chang, C. and Chia, Y. T., Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's, IEEE Trans. Electron Devices, 1987, ED-34(12), 2469.
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8. Hong, S. and Lee, K., Extraction of metallurgical effective channel length in LDD MOSFET's, IEEE Trans. Electron Devices, 1995, ED-42(8), 1461-1466.
9. Tsividis, Y. P., Operation and Modeling of the MOS Transistor, McGraw-Hill Book Company, New York, 1987.