Scaling theory in modern VLSI: Factors affecting interconnects, wire length, and clock speed

IEEE Circuits and Devices Magazine

Volumn 13, Issue 5, 1997, Pages 41-44

  Ferry, D K ^a   Akers, L A ^b  

^a Arizona State University   (United States)

^b UNIVERSITY OF TEXAS AT SAN ANTONIO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC WIRE; INTERCONNECTION NETWORKS; TIMING CIRCUITS;

CELL SIZE REDUCTION; SCALING THEORY;

VLSI CIRCUITS;

EID: 0031232996     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.621606     Document Type: Article

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