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Volumn 144, Issue 5, 1997, Pages 348-352

GRASS: An efficient gate re-assignment algorithm for inverter minimisation in post technology mapping

Author keywords

Logic synthesis; Networks; Technology mapping

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CONSTRAINT THEORY; ELECTRIC NETWORK SYNTHESIS; GATES (TRANSISTOR);

EID: 0031232861     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19971517     Document Type: Article
Times cited : (4)

References (12)
  • 1
    • 33746012950 scopus 로고
    • Algorithms for multi-level logic synthesis and optimization
    • DE MICHELI, G., SANGIOVANNI-VINCENTELLI, A.L., and ANTONGNETTI, (Eds.) Matrinus Nijhoff Publishers
    • BRAYTON, R.K.: 'Algorithms for multi-level logic synthesis and optimization' in DE MICHELI, G., SANGIOVANNI-VINCENTELLI, A.L., and ANTONGNETTI, (Eds.): 'Design systems for VLSI circuits' (Matrinus Nijhoff Publishers, 1987), pp. 197-248
    • (1987) Design Systems for VLSI Circuits , pp. 197-248
    • Brayton, R.K.1
  • 7
    • 0024142721 scopus 로고
    • Mapping properties of multi-level logic synthesis operations
    • LEGA, M.: 'Mapping properties of multi-level logic synthesis operations'. Proceedings of ICCD, 1988, pp. 257-260
    • (1988) Proceedings of ICCD , pp. 257-260
    • Lega, M.1
  • 8
    • 85061355883 scopus 로고
    • Technology mapping using boolean matching and don't care sets
    • MAILHOT, F., and DE MICHELI, G.: 'Technology mapping using boolean matching and don't care sets'. Proceedings of EDAC, 1990, pp. 212-216
    • (1990) Proceedings of EDAC , pp. 212-216
    • Mailhot, F.1    De Micheli, G.2
  • 10
    • 0027796616 scopus 로고
    • Inverter minimization in logic networks
    • JAIN, A., and BRYANT, R.E.: 'Inverter minimization in logic networks'. Proceedings of IEEE ICCAD, 1993, pp. 462-465
    • (1993) Proceedings of IEEE ICCAD , pp. 462-465
    • Jain, A.1    Bryant, R.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.