메뉴 건너뛰기




Volumn 2, Issue 4, 1997, Pages 76-102

Silicon microelectronics technology

(1)  Clemens, James T a  

a NONE

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; BIPOLAR TRANSISTORS; DEPOSITION; LITHOGRAPHY; OXIDATION; PASSIVATION; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING; VLSI CIRCUITS;

EID: 0031223839     PISSN: 10897089     EISSN: None     Source Type: Journal    
DOI: 10.1002/bltj.2084     Document Type: Article
Times cited : (34)

References (20)
  • 1
    • 0009409485 scopus 로고
    • Planar Silicon Transistors and Diodes
    • Mar.
    • J. A. Hoerni, "Planar Silicon Transistors and Diodes," IRE Trans, on Electron Devices, Vol. ED-8, No. 2, Mar. 1961, p. 178.
    • (1961) IRE Trans, on Electron Devices , vol.ED-8 , Issue.2 , pp. 178
    • Hoerni, J.A.1
  • 2
    • 7444264623 scopus 로고    scopus 로고
    • "Method and Apparatus for Controlling Electric Currents," U.S. Patent 1,745,175, filed Oct. 8, 1926, issued Jan. 28, 1930
    • J. E. Lilienfeld, "Method and Apparatus for Controlling Electric Currents," U.S. Patent 1,745,175, filed Oct. 8, 1926, issued Jan. 28, 1930.
    • Lilienfeld, J.E.1
  • 3
    • 7444266351 scopus 로고    scopus 로고
    • "Improvements in or Relating to Electrical Amplifiers and Other Control Arrangements and Devices," British Patent 439,457, filed Mar. 4, 1935, issued Dec. 6, 1935
    • O. Heil, "Improvements in or Relating to Electrical Amplifiers and Other Control Arrangements and Devices," British Patent 439,457, filed Mar. 4, 1935, issued Dec. 6, 1935.
    • Heil, O.1
  • 4
    • 7444250193 scopus 로고    scopus 로고
    • "Method for Making MIS Structures," U.S. Patent 3,475,234, filed Mar. 27, 1967, issued Oct. 28, 1969
    • R. E. Kerwin, D. L. Klein, and J. C. Sarace, "Method for Making MIS Structures," U.S. Patent 3,475,234, filed Mar. 27, 1967, issued Oct. 28, 1969.
    • Kerwin, R.E.1    Klein, D.L.2    Sarace, J.C.3
  • 5
    • 84938162176 scopus 로고
    • Cost Size Optima of Monolithic Integrated Circuits
    • B. T. Murphy, "Cost Size Optima of Monolithic Integrated Circuits," Proc. Inst. Electr. Eng., Vol. 52, 1964, pp. 1537-1545.
    • (1964) Proc. Inst. Electr. Eng. , vol.52 , pp. 1537-1545
    • Murphy, B.T.1
  • 8
    • 0018457005 scopus 로고
    • VLSI: Some Fundamental Challenges
    • Apr.
    • G. E. Moore, "VLSI: Some Fundamental Challenges," IEEE Spectrum, Vol. 16, No. 4, Apr. 1979, pp. 30-37.
    • (1979) IEEE Spectrum , vol.16 , Issue.4 , pp. 30-37
    • Moore, G.E.1
  • 10
    • 0000689282 scopus 로고
    • Single crystals of germanium and silicon - Basic to the transistor and integrated circuit
    • July
    • G. K. Teal, "Single crystals of germanium and silicon - basic to the transistor and integrated circuit," IEEE Trans. Electron Devices, Vol. ED-23, No. 7, July 1976, pp. 621-639.
    • (1976) IEEE Trans. Electron Devices , vol.ED-23 , Issue.7 , pp. 621-639
    • Teal, G.K.1
  • 11
    • 84944488621 scopus 로고
    • Stabilization of Silicon Surfaces by Thermally Grown Oxides
    • May
    • M. Atalla, E. Tannenbaum, and E. J. Scheibner, "Stabilization of Silicon Surfaces by Thermally Grown Oxides," Bell System Technical Journal, Vol. 38, No. 3, May 1959, pp. 749-783.
    • (1959) Bell System Technical Journal , vol.38 , Issue.3 , pp. 749-783
    • Atalla, M.1    Tannenbaum, E.2    Scheibner, E.J.3
  • 12
    • 1642621158 scopus 로고
    • General Relationship for the Thermal Oxidation of Silicon
    • Dec.
    • B. Deal and A. Grove, "General Relationship for the Thermal Oxidation of Silicon," J. Applied Physics, Vol. 36, No. 12, Dec. 1965, pp. 3770-3778.
    • (1965) J. Applied Physics , vol.36 , Issue.12 , pp. 3770-3778
    • Deal, B.1    Grove, A.2
  • 13
    • 3943104102 scopus 로고
    • Oxidation of Silicon by High-Pressure Steam
    • Feb.
    • J. Ligenza, "Oxidation of Silicon by High-Pressure Steam," J. Electrochem. Soc., Vol. 109, No. 2, Feb. 1962, pp. 73-76.
    • (1962) J. Electrochem. Soc. , vol.109 , Issue.2 , pp. 73-76
    • Ligenza, J.1
  • 14
    • 0018518071 scopus 로고
    • ESR centers, interface states, and oxide fixed charge in thermally oxidized silicon wafers
    • Sept.
    • P. J. Caplan, E. Poindexter, B. Deal, and R. Razouk, "ESR centers, interface states, and oxide fixed charge in thermally oxidized silicon wafers," J. Applied Physics, Vol. 50, No. 9, Sept. 1979, pp. 5847-5854.
    • (1979) J. Applied Physics , vol.50 , Issue.9 , pp. 5847-5854
    • Caplan, P.J.1    Poindexter, E.2    Deal, B.3    Razouk, R.4
  • 15
  • 20
    • 36549103511 scopus 로고
    • New approach to projection-electron lithography with demonstrated 0.1 urn linewidth
    • July 9
    • S. D. Berger and J. M. Gibson, "New approach to projection-electron lithography with demonstrated 0.1 urn linewidth," Appl. Phys. Lett., Vol. 57, No. 2, July 9, 1990, pp. 153-155.
    • (1990) Appl. Phys. Lett. , vol.57 , Issue.2 , pp. 153-155
    • Berger, S.D.1    Gibson, J.M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.