The economics of system-level testing

IEEE Design and Test of Computers

Volumn 14, Issue 3, 1997, Pages 51-58

  Farren, Des ^{a,c,d,e,f,g,h,i}   Ambler, Tony ^b  

^a HEWLETT PACKARD COMPANY   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^c MOTOROLA   (Ireland)

^d Digital Equipment   (United Kingdom)

^e Brunel University ^*

^f BRUNEL UNIVERSITY   (United Kingdom)

^g IEEE   (Ireland)

^h Mahon Industrial Estate ^*  (Ireland)

ⁱ MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; COST EFFECTIVENESS; ERROR CORRECTION; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; RELIABILITY; RISK ASSESSMENT;

OPEN LOOP ENVIRONMENT; SYSTEM LEVEL TESTING;

COMPUTER TESTING;

EID: 0031193121     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.605996     Document Type: Article

References (11)

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