-
1
-
-
84865944371
-
-
Mathworks, Inc., Natick, Mass., Nov.
-
"The Pentium Papers," Mathworks, Inc., Natick, Mass., Nov. 1994, http://www.mathworks.com/README.html.
-
(1994)
The Pentium Papers
-
-
-
2
-
-
3743098051
-
-
Tech. Report CSL-TR-94-647, Stanford University, Departments of Electrical Engineering and Computer Science, Stanford, Calif., Dec.
-
S.F. Oberman and M.J. Flynn, "Design Issues in Floating-Point Division," Tech. Report CSL-TR-94-647, Stanford University, Departments of Electrical Engineering and Computer Science, Stanford, Calif., Dec. 1994.
-
(1994)
Design Issues in Floating-Point Division
-
-
Oberman, S.F.1
Flynn, M.J.2
-
3
-
-
0027192467
-
New Algorithms and VLSI Architectures for SRT Division and Square Root
-
IEEE, Piscataway, N.J.
-
S.E. McQuillan, J.V. McCanny, and R. Hamill, "New Algorithms and VLSI Architectures for SRT Division and Square Root," Proc. 11th IEEE Symp. Computer Arithmetic, IEEE, Piscataway, N.J., 1993, pp. 80-86.
-
(1993)
Proc. 11th IEEE Symp. Computer Arithmetic
, pp. 80-86
-
-
McQuillan, S.E.1
McCanny, J.V.2
Hamill, R.3
-
4
-
-
33745088144
-
Area and Performance Tradeoffs in Floating-Point Division and Square Root Implementations
-
Sept.
-
P. Soderquist and M. Leeser, "Area and Performance Tradeoffs in Floating-Point Division and Square Root Implementations," ACM Computing Surveys, Vol. 28, No. 3, Sept. 1996, pp. 518-564.
-
(1996)
ACM Computing Surveys
, vol.28
, Issue.3
, pp. 518-564
-
-
Soderquist, P.1
Leeser, M.2
-
5
-
-
0026368492
-
A VLSI Architecture for Multiplication, Division, and Square Root
-
IEEE
-
S.E. McQuillan and J.V. McCanny, "A VLSI Architecture for Multiplication, Division, and Square Root," Proc. 1991 Int'l Conf. Acoustics, Speech and Signal Processing, IEEE, 1991, pp. 1205-1208.
-
(1991)
Proc. 1991 Int'l Conf. Acoustics, Speech and Signal Processing
, pp. 1205-1208
-
-
McQuillan, S.E.1
McCanny, J.V.2
-
6
-
-
3743094707
-
-
unpublished article, Aug. available upon request from author
-
W. Kahan, Using MathCAD 3.1 on a Mac, unpublished article, Aug. 1994; available upon request from author.
-
(1994)
Using MathCAD 3.1 on a Mac
-
-
Kahan, W.1
-
7
-
-
0023229767
-
Fast Multiply and Divide for a VLSI Floating-point Unit
-
IEEE
-
B.K. Bose et al., "Fast Multiply and Divide for a VLSI Floating-point Unit," Proc. Eighth IEEE Symp. Computer Arithmetic, IEEE, 1987, pp. 87-94.
-
(1987)
Proc. Eighth IEEE Symp. Computer Arithmetic
, pp. 87-94
-
-
Bose, B.K.1
-
9
-
-
0029216689
-
An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations
-
IEEE
-
P. Soderquist and M. Leeser, "An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations," Proc. 12th IEEE Symp. Computer Arithmetic, IEEE, 1995, pp. 132-139.
-
(1995)
Proc. 12th IEEE Symp. Computer Arithmetic
, pp. 132-139
-
-
Soderquist, P.1
Leeser, M.2
-
11
-
-
85037103633
-
Appendix A, Computer Arithmetic
-
J.L. Hennessy and D.A. Patterson, Morgan Kaufmann Publishers, San Francisco
-
D. Goldberg "Appendix A, Computer Arithmetic," in J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, San Francisco, 1990.
-
(1990)
Computer Architecture: A Quantitative Approach
-
-
Goldberg, D.1
-
13
-
-
0027189044
-
Very High Radix Division with Selection by Rounding and Prescaling
-
IEEE
-
M.D. Ercegovac, T. Lang, and P. Montuschi, "Very High Radix Division with Selection by Rounding and Prescaling," Proc. 11th IEEE Symp. Computer Arithmetic, IEEE, 1993, pp. 112-119.
-
(1993)
Proc. 11th IEEE Symp. Computer Arithmetic
, pp. 112-119
-
-
Ercegovac, M.D.1
Lang, T.2
Montuschi, P.3
-
14
-
-
0026259615
-
A Zero-Overhead Self-Timed 160-ns 54-b CMOS Divider
-
Nov.
-
T.E. Williams, "A Zero-Overhead Self-Timed 160-ns 54-b CMOS Divider," IEEE J. Solid-State Circuits, Vol. 26, No. 11, Nov. 1991, pp. 1651-1661.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, Issue.11
, pp. 1651-1661
-
-
Williams, T.E.1
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