A sparse memory access architecture for digital neural network lsis

IEICE Transactions on Electronics

Volumn E80-C, Issue 7, 1997, Pages 996-1001

  Aihara, Kimihisa ^a   Fujita, Osamu ^b   Uchimura, Kuniharu ^b  

^a NTT Network Service Systems Laboratories   (Japan)

^b NTT CORPORATION   (Japan)

Author keywords

Data driven; Digital lsi; Neural network; Perceptron

Indexed keywords

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; DIGITAL INTEGRATED CIRCUITS; LSI CIRCUITS; PARALLEL PROCESSING SYSTEMS;

SPARSE MEMORY ACCESS ARCHITECTURE;

NEURAL NETWORKS;

EID: 0031191572     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (5)

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2. H. Nakahira, S. Sakiyama, M. Murayama, T. Kouda, S. Maruno, and Y. Shimeki, A digital neuroprocessor using quantizer neurons, 1993 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 35-36, 1993.
3. Y. Kondo, Y. Koshiba, Y. Arima, M. Murasaki, T. Yamada, H. Amishiro, H. Shinihara, and H. Mori, A 1.2 GFLOPS neural network chip exhibiting fast convergence, 1994 IEEE International Solid-State Circuit Conference, Digests of Technical Paper, pp. 218-219, 1994.
4. K. Aihara, O. Fujita, and K. Uchimura, A sparse memory-access neural network engine with 96 parallel data-driven processing unit, 1995 IEEE International Solid-State Circuit Conference, Digests of Technical Paper, pp. 72-73, 1995.
5. F. Rosenblatt, Principles of neurodynamics, Spartan, 1961.