The impact of iron, copper, and calcium contamination of silicon surfaces on the yield of a MOS dram test process

Solid-State Electronics

Volumn 41, Issue 7, 1997, Pages 1021-1025

  Burte, E P ^a   Aderhold, W ^a  

^a FRAUNHOFER INSTITUTE FOR INTEGRATED CIRCUITS IIS   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CALCIUM; CAPACITORS; COPPER; DIELECTRIC PROPERTIES; ELECTRIC BREAKDOWN OF SOLIDS; IMPURITIES; IRON; RANDOM ACCESS STORAGE; SILICON WAFERS;

WAFER SURFACE CONTAMINATION;

MOS DEVICES;

EID: 0031189609     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(97)00016-6     Document Type: Article

References (3)

1. Tardif, F., et al., Proc. 2nd Int. Symp. on Ultra-clean Processing of Silicon Surfaces, 1994, ed. Marc Heyns, Acco Leuven, p. 309.
2. Keller, U., et al., Proc. 2nd Int. Symp. on Ultra-clean Processing of Silicon Surfaces, 1994, ed. Marc Heyns, Acco Leuven, p. 11.
3. Streckfuß, N., et al., ECS Proc., 1993, 93-15, p. 83.