Symbolic techniques for formally verifying industrial systems

Science of Computer Programming

Volumn 29, Issue 1-2, 1997, Pages 79-98

  Campos, Sérgio ^a   Clarke, Edmund M ^a   Minea, Marius ^a  

^a Carnegie Mellon University   (United States)

Author keywords

Binary decision diagrams; CTL; Futurebus+; PCI Local Bus; Quantitative timing analysis; SMV; Symbolic model checking; Temporal logic model checking

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; COMPUTER SYSTEMS; COMPUTER TESTING; ERROR CORRECTION; ERRORS; FORMAL LOGIC;

BINARY DECISION DIAGRAMS; QUANTITATIVE TIMING ANALYSIS; SYMBOLIC MODEL CHECKING; SYMBOLIC TECHNIQUES; TEMPORAL LOGIC MODEL CHECKING; VERIFICATION;

COMPUTER APPLICATIONS;

EID: 0031188120     PISSN: 01676423     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0167-6423(96)00030-5     Document Type: Article

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