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Volumn 25, Issue 1, 1997, Pages 248-259
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Design and evaluation of a DRAM-based shared memory ATM switch
a
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Author keywords
[No Author keywords available]
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Indexed keywords
BUFFER STORAGE;
COMPUTABILITY AND DECIDABILITY;
COMPUTER ARCHITECTURE;
LOCAL AREA NETWORKS;
MULTICHIP MODULES;
RANDOM ACCESS STORAGE;
RESPONSE TIME (COMPUTER SYSTEMS);
SWITCHING NETWORKS;
TELECOMMUNICATION TRAFFIC;
DYNAMIC RANDOM ACCESS MEMORY (DRAM);
SHARED MEMORY ASYNCHRONOUS TRANSFER MODE (ATM) SWITCH;
ASYNCHRONOUS TRANSFER MODE;
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EID: 0031169610
PISSN: 01635999
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/258623.258693 Document Type: Article |
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Times cited : (5)
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References (9)
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