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Volumn 32, Issue 6, 1997, Pages 890-897

Low power GaAs current-mode 1.2 Gb/s interchip interconnections

Author keywords

Current mode interconnections; Feedback circuits; Integrated circuit desing; Integrated circuit interconnections; Logic design; Multichip modules; Very high speed integrated circuits

Indexed keywords

AMPLIFIERS (ELECTRONIC); ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC WIRING; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MULTICHIP MODULES; SEMICONDUCTING GALLIUM ARSENIDE;

EID: 0031168459     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.585291     Document Type: Article
Times cited : (18)

References (9)
  • 1
    • 0002761217 scopus 로고
    • Power optimization techniques for high-speed GaAs logic
    • Gothenburg, Sweden
    • S. Long, "Power optimization techniques for high-speed GaAs logic," in Twelfth NORCHIP Seminar, Gothenburg, Sweden, 1994, pp. 93-105.
    • (1994) Twelfth NORCHIP Seminar , pp. 93-105
    • Long, S.1
  • 2
    • 0029533614 scopus 로고
    • Low power current mode multi-valued logic interconnect for high speed interchip communications
    • San Diego, CA
    • J. Q. Zhang, S. I. Long, F. H. Ho, and J. K. Madsen, "Low power current mode multi-valued logic interconnect for high speed interchip communications," in 17th IEEE GaAs IC Symp., San Diego, CA, 1995, pp. 327-330.
    • (1995) 17th IEEE GaAs IC Symp. , pp. 327-330
    • Zhang, J.Q.1    Long, S.I.2    Ho, F.H.3    Madsen, J.K.4
  • 3
    • 0026141225 scopus 로고
    • Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's
    • E. Seevinck, P. J. van Beers, and H. Ontrop, "Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's," IEEE J. Solid-State Circuits. vol. 26, no. 4, pp. 525-534, 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , Issue.4 , pp. 525-534
    • Seevinck, E.1    Van Beers, P.J.2    Ontrop, H.3
  • 5
    • 0017980692 scopus 로고
    • Static and dynamic noise margin in logic circuits
    • J. Lohstroh, "Static and dynamic noise margin in logic circuits," IEEE J. Solid-state Circuits, Vol. SC-14, no. 3, PP. 591-598, 1979.
    • (1979) IEEE J. Solid-state Circuits , vol.SC-14 , Issue.3 , pp. 591-598
    • Lohstroh, J.1
  • 6
    • 0016963360 scopus 로고
    • High speed integrated injection logic
    • C. Mulder and H. E. J. Wulms, "High speed integrated injection logic," IEEE J. Solid-State Circuits, vol. SC-11, no. 3, pp. 379-385, 1976.
    • (1976) IEEE J. Solid-State Circuits , vol.SC-11 , Issue.3 , pp. 379-385
    • Mulder, C.1    Wulms, H.E.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.