Impact of gate fan-in and fan-out limits on optoelectronic digital circuits

Applied Optics

Volumn 36, Issue 17, 1997, Pages 3927-3940

  Ji, Lianhua ^a   Heuring, V P ^a  

^a UNIVERSITY OF COLORADO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED LOGIC DESIGN; COMPUTER ARCHITECTURE; DIGITAL CIRCUITS; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; OPTICAL DATA PROCESSING; OPTICAL INTERCONNECTS;

CIRCUIT DELAY; LOGIC FUNCTIONS; OPTOELECTRONIC DIGITAL CIRCUITS; OPTOELECTRONIC GATES;

INTEGRATED OPTOELECTRONICS;

EID: 0031168227     PISSN: 1559128X     EISSN: 21553165     Source Type: Journal    
DOI: 10.1364/AO.36.003927     Document Type: Article

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