Circuit placement, chip optimization and wire routing for IBM IC technology

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 16, Issue 2-3, 1997, Pages 191-198

  Hathaway, D J ^a   Habra, R R ^a   Schanzenbach, E C ^a   Rothman, S J ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; ELECTRIC WIRING; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; ITERATIVE METHODS; OPTIMIZATION; TIMING CIRCUITS;

TIMING DERIVED CONSTRAINTS;

MICROPROCESSOR CHIPS;

EID: 0031167520     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1007943124807     Document Type: Article

References (16)