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Volumn 46, Issue 3, 1997, Pages 667-671

Built-in self-test design of current-mode algorithmic analog-to-digital converters

Author keywords

Algorithmic analog to digital (A D) converter; BIST design; Built in self test (BIST); Current mode; Self testability; Test generation

Indexed keywords

ANALOG TO DIGITAL CONVERSION; ELECTRONIC EQUIPMENT TESTING; ERROR DETECTION; LINEAR INTEGRATED CIRCUITS; MOS DEVICES; OPERATIONAL AMPLIFIERS; SWITCHING;

EID: 0031164176     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/19.585427     Document Type: Article
Times cited : (17)

References (12)
  • 1
    • 0025448207 scopus 로고
    • Built-in self-test (BIST) structure for analog circuits fault diagnosis
    • June
    • C. L. Wey, "Built-in self-test (BIST) structure for analog circuits fault diagnosis," IEEE Trans. Instrum. Meas., vol. 39, pp. 517-521, June 1990.
    • (1990) IEEE Trans. Instrum. Meas. , vol.39 , pp. 517-521
    • Wey, C.L.1
  • 2
    • 0026910792 scopus 로고
    • Built-in self-test (BIST) structures for analog circuit fault diagnosis with current test data
    • Aug.
    • C. L. Wey and S. Krishnan, "Built-in self-test (BIST) structures for analog circuit fault diagnosis with current test data," IEEE Trans. Instrum. Meas., vol. 41, pp. 535-539, Aug. 1992.
    • (1992) IEEE Trans. Instrum. Meas. , vol.41 , pp. 535-539
    • Wey, C.L.1    Krishnan, S.2
  • 3
    • 0030109962 scopus 로고    scopus 로고
    • Built-in self-test (BIST) design of high-speed carry-free dividers
    • Mar.
    • C. L. Wey, "Built-in self-test (BIST) design of high-speed carry-free dividers," IEEE Trans. VLSI Syst., vol. 4, pp. 141-145, Mar. 1996.
    • (1996) IEEE Trans. VLSI Syst. , vol.4 , pp. 141-145
    • Wey, C.L.1
  • 4
    • 0022737842 scopus 로고
    • Analog MOS integrated circuits - Certain new ideas, trends, and obstacles
    • June
    • Y. P. Tisividis, "Analog MOS integrated circuits - certain new ideas, trends, and obstacles," IEEE J. Solid-State Circuits, vol. SC-22, pp. 317-321, June 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.SC-22 , pp. 317-321
    • Tisividis, Y.P.1
  • 7
    • 0026106787 scopus 로고
    • An error-compensation A/D conversion technique
    • Feb.
    • H. T. Yung and K. S. Chao, "An error-compensation A/D conversion technique," IEEE Trans. Circuits Syst., vol. 38, pp. 187-195, Feb. 1991.
    • (1991) IEEE Trans. Circuits Syst. , vol.38 , pp. 187-195
    • Yung, H.T.1    Chao, K.S.2
  • 8
    • 0025400116 scopus 로고
    • A ratio-independent algorithmic analog-to-digital converter combining current mode and dynamic techniques
    • Mar.
    • D. G. Nairn and C. S. Salama, "A ratio-independent algorithmic analog-to-digital converter combining current mode and dynamic techniques," IEEE Trans. Circuits Syst., vol. 37, pp. 319-325, Mar. 1990.
    • (1990) IEEE Trans. Circuits Syst. , vol.37 , pp. 319-325
    • Nairn, D.G.1    Salama, C.S.2
  • 9
    • 0012931529 scopus 로고
    • Test generation and concurrent error detection in current-mode A/D converters
    • Baltimore, MD, Sept.
    • S. Krishnan, S. Sahli, and C. L. Wey, "Test generation and concurrent error detection in current-mode A/D converters," Proc. IEEE Int. Test Conf. (ITC). Baltimore, MD, Sept. 1992, pp. 312-320.
    • (1992) Proc. IEEE Int. Test Conf. (ITC) , pp. 312-320
    • Krishnan, S.1    Sahli, S.2    Wey, C.L.3
  • 10
    • 0002044128 scopus 로고
    • Design of concurrent error detectable current-mode A/D converters for real-time applications
    • July
    • C. L. Wey, S. Krishnan, and S. Sahli, "Design of concurrent error detectable current-mode A/D converters for real-time applications," Analog Integrated Circuits Signal Processing, pp. 65-74, July 1993.
    • (1993) Analog Integrated Circuits Signal Processing , pp. 65-74
    • Wey, C.L.1    Krishnan, S.2    Sahli, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.