Efficient shared-memory support for parallel graph reduction

Future Generation Computer Systems

Volumn 12, Issue 6, 1997, Pages 481-503

  Bennett, Andrew J ^a,b   Kelly, Paul H J ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

^b UNIVERSITY COLLEGE LONDON   (United Kingdom)

Author keywords

Cache organisation; Declarative languages; Shared memory; Simulation

Indexed keywords

BUFFER STORAGE; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SIMULATION; COMPUTER SYSTEMS PROGRAMMING; INTERCONNECTION NETWORKS; NETWORK PROTOCOLS; OPTIMIZATION; SYNCHRONIZATION;

CACHE COHERENCY; FUNCTIONAL PROGRAMMING LANGUAGES; PARALLEL GRAPH REDUCTION (PGR); SHARED MEMORY SYSTEMS;

PARALLEL PROCESSING SYSTEMS;

EID: 0031162002     PISSN: 0167739X     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-739X(96)00019-2     Document Type: Article

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