Impact of boron penetration at P+-poly/gate oxide interface on deep-submicron device reliability for dual-gate CMOS technologies

IEEE Electron Device Letters

Volumn 18, Issue 5, 1997, Pages 215-217

  Hao, Ming Yin ^a   Nayak, Deepak ^a   Rakkhit, Rajat ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BORON; ELECTRIC BREAKDOWN OF SOLIDS; INTERFACES (MATERIALS); ION IMPLANTATION; RELIABILITY;

BORON PENETRATION; IMPLANT ENERGY; RAPID THERMAL ANNEALING TEMPERATURE;

CMOS INTEGRATED CIRCUITS;

EID: 0031146101     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.568770     Document Type: Article

References (6)

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3. +-gate p-channel MOSFET's with fluorine incorporation," IEEE Trans. Electron Devices, vol. 39, p. 1687, 1992.
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