2-V/100-ns 1T/1C nonvolatile ferroelectricmemory architecture with bitline-driven read scheme and nonrelaxation reference cell

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 5, 1997, Pages 649-654

  Hirano, Hiroshige ^a,b,c   Honda, Toshiyuki ^a,b,d   Moriwaki, Nobuyuki ^a,c   Nakakuma, Tetsuji ^a,b,e   Inoue, Atsuo ^a,b,f   Nakane, George ^a,b,g   Chaya, Shigeo ^a,b,h   Sumi, Tatsumi ^a,b,i,j,k,l  

^a PANASONIC CORPORATION   (Japan)

^b Osaka University ^*

^c OSAKA UNIVERSITY   (Japan)

^d OKAYAMA UNIVERSITY   (Japan)

^e KYUSHU UNIVERSITY   (Japan)

^f KANSAI UNIVERSITY   (Japan)

^g Osaka Prefecture University   (Japan)

^h SHINSHU UNIVERSITY   (Japan)

ⁱ WASEDA UNIVERSITY   (Japan)

^j Matsushita Electronics Corpration   (Japan)

^k Device Development Department I   (Japan)

^l IEEE

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Author keywords

1T 1C cell; Ferroelectric; Memory; Nonvolatile

Indexed keywords

CAPACITORS; CELLULAR ARRAYS; ELECTRIC CONTROL EQUIPMENT; FERROELECTRIC DEVICES; INTEGRATED CIRCUIT LAYOUT; RANDOM ACCESS STORAGE; SECONDARY BATTERIES; TRANSISTORS;

FERROELECTRIC RANDOM ACCESS MEMORY (FERAM) ARCHITECTURE; MICROCONTROLLERS;

NONVOLATILE STORAGE;

EID: 0031145165     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.568826     Document Type: Article

References (3)

1. H. Hirano, T. Honda, S. Chaya, T. Fukumoto, and T. Sumi, "2 V/100 ns embedded flash EEPROM circuit technology," IEICE Trans. Electron., vol. E79-C, no. 6, pp. 825-831, June 1996.
2. T. Sumi, N. Moriwaki, G. Nakane, T. Nakakuma, Y. Judai, Y. Uemoto, Y. Nagano, S. Hayashi, M. Azuma, E. Fujii, S. Katsu, T. Otsuki, L. McMillan, C. A. Paz de Araujo, and G. Kano, "A 256Kb nonvolatile ferroelectric memory at 3 V and 100 ns," in ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 1994.
3. H. Koike, T. Otsuki, T. Kimura, M. Fukumura, Y. Hayashi, Y. Maejima, K. Amanuma, N. Tanabe, T. Matsuki, S. Saito, T. Takeuchi, S. Kobayashi, T. Kunio, T. Hase, Y. Miyasaka, N. Shohata, and M. Takada, "A 60 ns 1 Mb nonvolatile ferroelectric memory with non-driven cell plate line write/read scheme," ISSCC Dig. Tech. Papers, pp. 368-369, Feb. 1996.