Symbolic FSM traversais based on the transition relation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 5, 1997, Pages 448-457

  Cabodi, Gianpiero ^a   Camurati, Paolo ^b  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF UDINE   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTATIONAL METHODS; DATA STORAGE EQUIPMENT; DECISION THEORY; FINITE AUTOMATA;

BINARY DECISION DIAGRAMS (BDD); FINITE STATE MACHINES (FSM);

SEQUENTIAL CIRCUITS;

EID: 0031143141     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.631208     Document Type: Article

References (35)

1. H. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. SangiovanniVincentelli, "Implicit enumeration of finite state machines using BDD's," in Proc. IEEE ICCAD'90, Nov. 1990, pp. 130-133.
2. J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill, "Symbolic model checking for sequential circuit verification," IEEE Trans. Computer-Aided Design, vol. 13, pp. 401-4124, Apr. 1994.
3. G. Cabodi and P. Camurati, "Exploiting cofactoring for efficient FSM symbolic traversal based on the transition relation," in Proc. IEEE ICCD'93, Oct. 1993, pp. 299-303.
4. W. Wolf, "The FSM network model for behavioral synthesis of controldominated machines," in Proc. ACM/IEEE DAC'90, June 1990, pp. 692-697.
5. C. Pixley, "A computational theory and implementation of sequential hardware equivalence," in AMS/DIMACS Ser. Discrete Math, and Theoretical Comput. Sci., vol. 3, 1991, pp. 293-320.
6. C. Pixley and G. Beihl, "Calculating resetability and reset sequences," in Proc. IEEEICCAD'91, Nov. 1991, pp. 376-379.
7. C. Pixley, S.-W. Jeong, and G. D. Hachtel, "Exact calculation of synchronization sequences based on binary decision diagrams," in Proc. ACM/IEEE DAC'92, June 1992, pp. 614-619.
8. J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill, "Sequential circuit verification using symbolic model checking," in DAC27: ACM/IEEE Design Automation Conf., Orlando, FL, June 1990, pp. 46-51.
9. H. Cho, G. D. Hachtel, and F. Somenzi, "Fast sequential ATPG based on implicit state enumeration," in Proc. IEEE ITC'91, Sept. 1991, pp. 67-74.
10. H. Cho, S.-W. Jeong, F. Somenzi, and C. Pixley, "Synchronization sequences and symbolic traversal techniques in test generation," JETTA, vol. 4, pp. 19-31, Feb. 1993.
11. H. Cho, G.cD. Hachtel, and F. Somenzi, "Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration," IEEE Trans. Computer-Aided Design, vol. 12, pp. 935-945, July 1993.
12. G. Cabodi, P. Camurati, F. Corno, P. Prinetto, and M. Sonza Reorda, "An approach to sequential circuit diagnosis based on formal verification techniques," JETTA, vol. 4, pp. 11-17, Feb. 1993.
13. S. H. Hwang and A. R. Newton, "An efficient verifier for finite state machines," IEEE Trans. Computer-Aided Design, vol. 10, pp. 326-334, Mar. 1991.
14. O. Coudert, C. Berthet, and J. C. Madre, "Verification of sequential machines based on symbolic execution," in Lecture Notes in Computer Science 407. Springer-Verlag, 1989, pp. 365-373.
15. Verification of sequential machines using Boolean function vectors," in Proc. IFIP Int. Workshop "Applied Formal Methods for Correct VLSI Design," vol. 1, Nov. 1989, pp. 111-128.
16. H. Cho, G. Hachtel, S. W. Jeong, B. Plessier, E. Schwarz, and F. Somenzi, "ATPG aspects of FSM verification," in Proc. IEEE ICCAD'90, Nov. 1990, pp. 134-137.
17. O. Coudert and J. C. Madre, "Verifying temporal properties of sequential machines without building the state diagrams," in Proc. CAV'90, June 1990, pp. 75-84.
18. T. Filkorn, "A method for symbolic verification of synchronous circuits," in Proc. IFIP CHDL'91, Apr. 1991, pp. 229-239.
19. S. Krischer, "The backward walk approach in FSM verification," in Proc. IFIP CHDL'93, Apr. 1993, pp. 143-150.
20. E. Cerny and M. A. Marin, "An approach to unified methodology of combinational switching circuits," IEEE Trans. Comput., vol. C26, pp. 745-756, Aug. 1986.
21. R. E. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Trans. Comput., vol. C35, pp. 677-691, Aug. 1986.
22. K. S. Brace, R. L. Rudell, and R. E. Bryant, "Efficient implementation of a BDD package," in Proc. ACM/IEEE DAC'90, June 1990, pp. 40-45.
23. R. E. Bryant, "Symbolic Boolean manipulation with ordered binarydecision diagrams," ACM Computing Surveys, vol. 24, pp. 293-318, Sept. 1992.
24. O. Coudert and J. C. Madre, "A unified framework for the formal verification of sequential circuits" in Proc. IEEE ICCAD '90, Nov. 1990, pp. 126-129.
25. Symbolic computation of the valid states of the sequential machine: Algorithms and discussion," in Proc. 1991 Int. Workshop Formal Methods in VLSI Design, Jan. 1991.
26. J. R. Burch, E. M. Clarke, and D. E. Long, "Representing circuits more efficiently in symbolic model checking," in Proc. ACM/IEEE DAC'91, June 1991, pp. 403-407.
27. Z. Kohavi, Switching and Finite Automata Theory, 2nd ed., Comput. Sci. Ser. New York: McGraw-Hill, 1978.
28. F. M. Brown, Boolean Reasoning: The Logic of Boolean Equations. Boston: Kluwer Academic, 1990.
29. D. Geist and I. Beer, "Efficient model checking by automated ordering of transition relation partitions," in Proc. CAV'94, June 1994, pp. 299-310.
30. R. K. Ranjan, A. Aziz, R. K. Brayton, B. Plessier, and C. Pixley, "Efficient BDD algorithms for FSM synthesis and verification," presented in IWLS'95, May 1995, poster presentation.
31. F. Somenzi, "CUDD: CU decision diagram package-Release 1.0.4," Tech. Rep., Dep. Elect. Comput. Eng., Univ. Colorado, Boulder, Nov. 1995.
32. F. Brglez, D. Bryan, and K. Kozmiriski, "Combinatorial profiles of sequential benchmark circuits," in Proc. IEEE ISCAS'89, May 1989, pp. 1929-1934.
33. MCNC private communication.
34. S. Yang, "Logic synthesis and optimization benchmarks user guide version 3.0," MCNC Rep., Research Triangle Park, NC, Jan. 1991.
35. H. Cho, G. D. Hachtel, E. Macii, M. Poncino, K. Ravi, and F. Somenzi, "Approximate finite state machine traversal: Extensions and new results," presented at IWLS95, Lake Tahoe, CA, May 1995.