Optimal cache usage for separable image processing algorithms on general purpose workstations

Signal Processing

Volumn 59, Issue 1, 1997, Pages 113-122

  Schutte, Klamer ^a   Van Kempen, Geert M P ^b  

^a TNO   (Netherlands)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Cache; Fast Fourier transform; General purpose workstations; Memory hierarchy; Separable image processing

Indexed keywords

ALGORITHMS; BUFFER STORAGE; COMPUTER WORKSTATIONS; DATA PROCESSING; FAST FOURIER TRANSFORMS;

DATA CACHE UTILIZATION; SUN WORKSTATIONS;

IMAGE PROCESSING;

EID: 0031141174     PISSN: 01651684     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0165-1684(97)00041-8     Document Type: Article

References (14)

1. R.C. Agarwal, F.G. Gustavson, M. Zubair, Improving performance of linear algebra algorithms for dense matrices, using algorithmic prefetch, IBM J. Res. Devel. 38 (1994) 265-275.
2. B. Alperen, L. Carter, E. Feig, T. Selker, The uniform memory hierarchy model of computation, Algorithmica 12 (1994) 72-109.
3. D.W. Dobberpuhl et al., A 200 MHz 64-bit dual-issue CMOS Microprocessor, DEC Technical J. (Special Issue) 4 (4) (1992) 1-15.
4. S.G. Dykes, X. Zhang, Y. Zhou, H. Yang, Communication and computation patterns of large scale image convolutions on parallel architectures, Proc. 8th Internat. Conf. on Parallel Processing Symposium, Cancun, Mexico, 1994, pp. 926-931.
5. F.C.A. Groen, R.J. Ekkers, R. de Vries, Image processing with personal computers, Signal Processing 15 (3) (1988) 279-291.
6. J. Heinrich, MIPS R4000 Microprocessor User's Manual, 2nd ed., Mips Technologies Inc. Mountain View, California, CA, 1994.
7. J.L. Hennessy, D.A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, Palo Alto, CA, 1990.
8. M.S. Lam, E.E. Rothberg, M.E. Wolf, The cache performance and optimizations of blocked algorithms, in: Internat. Conf. on Architectural Support for Programming Languages and Operating Systems - ASPLOS, Vol. 26, ACM, New York, NY, 1991, pp. 63-74.
9. P. Ling, A set of high-performance level 3 BLAS structured and tuned for the IBM 3090 VF and implemented in Fortran 77, J. Supercomput. 7 (1993) 323-355.
10. Sun Microsystems, The SuperSparc Microprocessor, Technical White Paper, Sun Microsystems Computer Corporation Mountain View, California, CA, May 1992.
11. Sun Microsystems, The ultraSparc processor, Technology White Paper, Sun Microsystems Computer Corporation Mountain View, California, CA, November 1995.
12. B. Tsutom Wada, A virtual memory system for picture processing, Comm. ACM 27 (1994) 444-454.
13. C.M. Wittenbrink, A.K. Somani, Cache tiling for high performance morphological image processing, Machine Vision Appl. 7 (1993) 12-22.
14. C.R. Moore, PowerPC 601 Microprocessor, Proc. COMPCON, San Francisco, CA, February 1993, pp. 109-116.