Partially depleted SOI NMOSFET's with self-aligned polysilicon gate formed on the recessed channel region

IEEE Electron Device Letters

Volumn 18, Issue 5, 1997, Pages 184-186

  Lee, Jong Ho ^a,b   Shin, Hyung Cheol ^a,c   Kim, Jong June ^d   Park, Choon Bae ^a,b   Park, Young June ^a,d  

^a IEEE   (South Korea)

^b Wonkwang University   (South Korea)

^c Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^d Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC BREAKDOWN OF SOLIDS; ELECTRIC CURRENT MEASUREMENT; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY;

POLYSILICON GATE; RECESSED CHANNEL REGION;

MOSFET DEVICES;

EID: 0031140719     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.568756     Document Type: Article

References (10)

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