Quick address detection of anomalous memory cells in a flash memory test structure

IEEE Transactions on Semiconductor Manufacturing

Volumn 10, Issue 2, 1997, Pages 196-200

  Himeno, Toshihiko ^b   Hazama, Hiroaki ^b   Yaegashi, Toshitake ^b   Sakui, Koji ^a,b   Kanda, Kazushige ^b   Itoh, Yasuo ^b   Miyamoto, Jun Ichi ^b  

^a IEEE

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING;

FLASH MEMORY CELLS; MULTIADDRESS SCANNING SCHEME (MASS); QUICK ADDRESS DETECTION; VOLTAGE DISTRIBUTION MONITOR CIRCUITS (VTDM);

DATA STORAGE EQUIPMENT;

EID: 0031140696     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.572068     Document Type: Article

References (4)

1. T. C. Ong et al., "Erratic erase in etox flash memory array," in Proc. Symp. VLSI Tech. Dig., 1993, p. 83.
2. T. Himeno et al., "New technique for measuring threshold voltage distribution in Flash EEPROM devices," in Proc. ICMTS, 1995, pp. 283-287.
3. T. Himeno et al., "Novel threshold voltage distribution measuring technique for Flash EEPROM devices," IEICE Trans. Electron., vol.E79-C, no. 2, pp. 145-151.
4. T. Himeno et al., "A quick address detection of an anomalous memory cell for Flash EEPROM," in Proc. ICMTS, 1996, pp. 195-199.