Performance models for the processor farm paradigm

IEEE Transactions on Parallel and Distributed Systems

Volumn 8, Issue 5, 1997, Pages 475-489

  Wagner, Alan S ^a,b   Sreekantaswamy, Halsur V ^c   Chanson, Samuel T ^a,d  

^a IEEE   (Canada)

^b UNIVERSITY OF BRITISH COLUMBIA   (Canada)

^c NORTEL NETWORKS   (Canada)

^d HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Master slave; Message passing architecture; Network flow; Parallel programming paradigms; Performance evaluation; Processor farm; Tree networks

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS; OPTIMIZATION; SUBROUTINES;

PERFORMANCE EVALUATION MODELS; PROCESSOR FARM PARADIGM; TREE STRUCTURED SUBNETWORKS;

PARALLEL PROCESSING SYSTEMS;

EID: 0031139523     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.598275     Document Type: Article

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