Noise margin enhancement in GaAs ROM's using current mode losic

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 4, 1997, Pages 592-597

  Lopez J F ^a   Sarmiento, R ^a   Eshraghian, K ^b   Nunez A ^a  

^a UNIVERSITY OF LAS PALMAS DE GRAN CANARIA   (Spain)

^b EDITH COWAN UNIVERSITY   (Australia)

Author keywords

Current mode logic; Gallium materials devices; Logic design; MESFET integrated circuits; Semiconductor memories; Very high speed integrated circuits

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LOGIC CIRCUITS; LOGIC DESIGN; MESFET DEVICES; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR STORAGE; SPURIOUS SIGNAL NOISE;

CMOS TECHNOLOGY; CURRENT MODE LOGIC; NOISE MARGIN ENHANCEMENT; VERY HIGH SPEED INTEGRATED CIRCUITS;

ROM;

EID: 0031122931     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.563683     Document Type: Article

References (11)

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