Architectural study of a block-recursive motion estimation algorithm

Real-Time Imaging

Volumn 3, Issue 2, 1997, Pages 111-128

  Charot, François ^a   Labit, Claude ^a   Lemonnier, Pascal ^a  

^a CAMPUS DE BEAULIEU   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; CONVERGENCE OF NUMERICAL METHODS; ESTIMATION; IMAGE CODING; IMAGE COMPRESSION; ITERATIVE METHODS; PARALLEL PROCESSING SYSTEMS; PERFORMANCE; REAL TIME SYSTEMS;

BLOCK MATCHING; BLOCK RECURSIVE ALGORITHM; DETERMINISTIC RELAXATION; MOTION COMPENSATION; MOTION ESTIMATION; QUADTREE REGION SPLITTING;

ALGORITHMS;

EID: 0031122134     PISSN: 10072014     EISSN: None     Source Type: Journal    
DOI: 10.1006/rtim.1996.0051     Document Type: Article

References (24)

1. SOS-THOMSON (1991) Data Book: STI3220 Motion Estimation Processor.
2. LSI LOGIC CCITT (1992) Data Book: Video Compression Chipset.
3. Artieri, A. & Jutand, F. (1989) A versatile and powerful chip for real time motion estimation. In ICASSP '89, volume 4, pp. 2453-2456, Glasgow, Scotland.
4. Barzic, R., Bouville, C., Charot, F., Le Fol, G., Lemonnier, P. & Wagner, C. (1995) MOVIE: A building block for the design of real time simulator of moving pictures compression algorithms. In Int. Conf. on Application Specific Array Processors - ASAP '95, Strasbourg, July.
5. Brofferio, S., Monti, M. & Taliercio, M. (1990) VLSI recursive motion estimator chip set. In Proc. of the IEEE Symposium on Circuits and Systems, volume 1, pp. 57-60, New Orleans, Lousiana, May.
6. De Vos, L. & Stegherr, M. (1989) Parameterizable VLSI architecture for the full-search block matching algorithm. IEEE Trans. Circuits and Systems, 36(10): 1309-1316.
7. ETSI (European Telecommunication Standards Institute) (1989) Specification of Components TV Codecs 32-45 Mbit/s. Technical report, December.
8. Frimout, E. D., Driessen, J. N. & Depreterre, E. F. (1992) Parallel architecture for a pel-recursive motion estimation algorithm. IEEE Trans. Circuits and Systems for Video Technology, 2(2): 159-168.
9. Hsieh, C.-H. & Lin, T.-P. (1992) VLSI architecture for block-matching motion estimation algorithm. IEEE Trans. Circuits and Systems for Video Technology, 2(2): 169-175.
10. Jain, J. R. & Jain, A. K. (1981) Displacement measurement and its application in interframe image coding. IEEE Trans. Comm., 29(12): 1799-1808.
11. Karathanasis, H. C. & Vlontzos, J. A. (1993) VLSI architectures for accurate motion and disparity estimation using full-search block-matching and edge preserving non-linear smoothing. In VLSI Signal Processing VI, pp. 75-83.
12. Kim, R. C. & Lee, S. U. (1989) A VLSI architecture for a pel recursive motion estimation algorithm. IEEE Trans. Circuits and Systems, 36(10): 1291-1300.
13. Koga, T., Linuma, K., Hirano, A., Lijima, Y. & Ishiguro, T. (1981) Motion compensated interframe coding for video conferencing. In Proc. National Telecommunication Conference, pp. G5.3.1-G5.3.5, New Orleans, Lousiana, November.
14. Komarek, T. & Pirsch, P. (1989) Array architecture for block matching algorithm. IEEE Trans. Circuits and Systems, 36(10): 1301-1308.
15. Labit, C. & Nicolas, H. (1991) Compact motion representation based on global features for semantic image sequence coding. In Proc. SPIE VCIP '91, Boston, November.
16. Le Gall, D. (1991) MPEG: A video compression standard for multimedia applications. Comm. of the ACM, 34(4): 46-58.
17. Liuou, M. (1991) Overview of the p×64 kbit/s video coding standard. Comm of the ACM, 34(4): 59-63.
18. Netravali, A. N. & Robbins, J. D. (1979) Motion-compensated television coding: part I. The Bell System Technical Journal, 58(3): 631-670.
19. Nicolas, H. (1992) Hiérarchie de modèles de mouvement et méthodes d'estimation associées, Application an codage de séquences d'images. PhD thesis, Université de Rennes I, Rennes, France.
20. Nicolas, H. & Labit, C. (1992) Region-based motion estimation using deterministic relaxation schemes for image sequence coding. In ICASSP '92, San Francisco, California.
21. Pirsch, P. & Komarek, T. (1988) VLSI Architectures for block matching algorithms. In Proc. SPIE VCIP '88, pp. 882-891.
22. Puri, A. (1993) Video coding using the MPEG-2 compression standard. In Proc. SPIE VCIP, vol. 2094, pp. 1701-1713, Cambridge, MA.
23. Srinivasan, R. & Rao, K. R. (1985) Predictive coding based on efficient motion estimation. IEEE Trans Communications, 33(8): 888-896.
24. Yang, K.-M., Sun, M.-T. & Wu, L. (1989) A family of VLSI design for the motion compensation block-matching algorithm. IEEE Trans. Circuits and Systems, 36(10): 1317-1325.