Arithmetic Boolean Expression Manipulator Using BDDs

Formal Methods in System Design

Volumn 10, Issue 2-3, 1997, Pages 221-242

  Minato, Shin Ichi ^a  

^a NTT CORPORATION   (Japan)

Author keywords

BDD; Boolean expression; Boolean function; Combinatorial problem; LSI CAD

Indexed keywords

ALGORITHMS; COMBINATORIAL MATHEMATICS; COMPUTATIONAL METHODS; DATA STRUCTURES; MATHEMATICAL OPERATORS; PROBLEM SOLVING; SYSTEMS ANALYSIS; VLSI CIRCUITS;

ARITHMETIC BOOLEAN EXPRESSION MANIPULATOR; BINARY DECISION DIAGRAMS (BDD);

BOOLEAN FUNCTIONS;

EID: 0031119337     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008643722423     Document Type: Article

References (20)

1. S. Akers, "Binary decision diagrams," IEEE Trans. Comput., Vol. C-27, No. 6, pp. 509-516, June 1978.
2. I. Bahar, E. Frohm, C. Gaona, G. Hachtel, W. Macil, A. Pardo, and F. Somenzi, "Algebraic decision diagrams and their applications," Proc. IEEE/ACM ICCAD'93, pp. 188-191, Nov. 1993.
3. K. Brace, R. Rudell, and R. Bryant, "Efficient implementation of a BDD package," ACM/IEEE Proc. 27th DAC, pp. 40-45, June 1990.
4. R. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Trans. Comput., Vol. C-35, No. 8, pp. 677-691, Aug. 1986.
5. R. Bryant, "Symbolic Boolean manipulation with ordered binary decision diagrams," CMU CS Technical Report, No. CMU-CS-92-160, July 1992.
6. J. Burch, E. Clarke, K. McMillan, and D. Dill, "Sequential circuit verification using symbolic model checking," Proc. ACM/IEEE DAC'90, pp. 618-624, June 1992.
7. E. Clarke, K. McMillan, X. Zhao, M. Fujita, and J. Yang, "Spectral transforms for large Boolean functions with applications to technology mapping," Proc. ACM/IEEE DAC'93, pp. 54-60, June 1993.
8. M. Fujita, Y. Matsunaga, and T. Kakuda, "On variable ordering of binary decision diagrams for the application of multi-level logic synthesis," Proc. the European Conference on Design Automation, pp. 50-54, 1991.
9. G. Hachtel, E. Macii, A. Pardo, and F. Somenzi, "Probabilistic analysis of large finite state machines," Proc. ACM/IEEE DAC'94, pp. 270-275, June 1994.
10. S. Jeong and F. Somenzi, "A new algorithm for the binate covering problem and its application to the minimization of Boolean relations," Proc. IEEE ICCAD'92, pp. 417-420, Nov. 1992.
11. B. Lin and F. Somenzi, "Minimization of symbolic relations," Proc. IEEE ICCAD'90, pp. 88-91, Nov. 1990.
12. Y. Matsunaga and M. Fujita, "Multi-level logic optimization using binary decision diagrams," Proc. ICCAD'89, pp. 556-559, Nov. 1989.
13. S. Minato, "Minimum-width method of variable ordering for binary decision diagrams," IEICE Jpn. Trans. Fundamentals, Vol. E75-A, No. 3, pp. 392-399, March 1992.
14. S. Minato, "Fast generation of irredundant sum-of-products forms from binary decision diagrams," Proceedings of the Synthesis and Simulation Meeting and International Interchange (SASIMI'92, Japan), pp. 64-73, March 1992.
15. S. Minato, N. Ishiura, and S. Yajima, "Fast tautology checking using shared binary decision diagram-benchmark results," Proc. IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, pp. 580-584, Nov. 1989.
16. S. Minato, N. Ishiura, and S. Yajima, "Symbolic simulation using shared binary decision diagram," Record of 1989 IEICE National Convention, SA-7-5, pp. 1.206-1.207, Sept. 1989 (in Japanese).
17. S. Minato, N. Ishiura, and S. Yajima, "Shared binary decision diagram with attributed edges for efficient Boolean function manipulation," ACM/IEEE Proc. 27th DAC, pp. 52-57, June 1990.
18. T. Miyazaki, "Boolean-based formulation for data path synthesis," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'92), pp. 201-205, Dec. 1992.
19. R. Rudell, "Dynamic variable ordering for ordered binary decision diagrams," Proc. IEEE/ACM ICCAD'93, pp. 42-47, Nov. 1993.
20. A. Takahara, "A timing analysis method for logic circuits," Record of 1993 IEICE National Convention, A-120, pp. 1-120, March 1993 (in Japanese).