Symbolic computation tree logic model checking of time Petri nets

Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)

Volumn 80, Issue 4, 1997, Pages 11-20

  Okawa, Yasukichi ^a   Yoneda, Tomohiro ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

CTL; Formal verification; Region; Symbolic model checking; Time Petri nets

Indexed keywords

ALGORITHMS; EQUIVALENCE CLASSES; MATHEMATICAL MODELS; PETRI NETS; REAL TIME SYSTEMS; STATE SPACE METHODS; TREES (MATHEMATICS);

COMPUTATION TREE LOGIC (CTL) MODEL; SYMBOLIC MODEL CHECKING;

ELECTRIC NETWORK ANALYSIS;

EID: 0031118998     PISSN: 10420967     EISSN: None     Source Type: Journal    
DOI: 10.1002/(sici)1520-6440(199704)80:4<11::aid-ecjc2>3.0.co;2-7     Document Type: Article

References (16)

1. E. M. Clarke, E. A. Emerson, and A. P. Sistla. Automatic verification of finite-state concurrent systems using temporal-logic specification. ACM Trans. on Programming Languages and Systems, 8, No. 2, pp. 244-263 (1986).
2. 20 states and beyond. Academic Press, 98, No. 2, pp. 142-170 (1992).
3. R. Alur and D. Dill. The theory of timed automata. LNCS 443 (17th ICALP), pp. 322-335 (1990).
4. T. Henzinger, Z. Manna, and A. Pnueli. Timed transition system. LNCS 600, pp. 226-251 (1992).
5. P. Merlin and D. J. Faber. Recoverability of communication protocols. IEEE Trans. on Communication, COM-24, No. 9 (1976).
6. T. Henzinger, X. Nicollin, J. Sifakis, and S. Yovine. Symbolic model checking for real-time systems. 7th IEEE LICS (1992).
7. R. Alur, C. Courcoubetis, and D. Dill. Model-checking for real-time systems. Proc. 5th IEEE LICS (1990).
8. T. Rokicki. Representing and Modeling Circuits. Ph.D. Thesis, Stanford University (1993).
9. B. Berthomieu and M. Diaz. Modeling and verification of time dependent systems using time Petri nets. IEEE Trans. on Software Eng., 17, No. 3, pp. 259-273 (1991).
10. T. Yoneda, A. Shibayama, H. Schlingloff, and E. M. Clarke. Efficient verification of parallel real-time systems. LNCS 697 Computer Aided Verification, pp. 321-332 (1993).
11. T. Henzinger, X. Nicollin, J. Sifakis, and S. Yovine. Symbolic model checking for real-time systems. Information and Computation, 111, pp. 193-244 (1994).
12. S. V. Campos and E. M. Clarke. Real-time symbolic model checking for discrete time models. Proc. First AMAST International Workshop in Real-Time Systems (1993).
13. T. Yoneda and Y. Okawa. Discrete analysis of time Petri nets. Proc. of PRFTS95, pp. 224-229 (1995).
14. D. E. Long. BDD Library Man Page (1993).
15. K. Nakane and T. Yoneda. Efficient model checking for linear-time temporal logic. Technical Report IEICE, Japan, FTS93, No. 47, pp. 65-72 (1993).
16. K. Hamaguchi, H. Hiraishi, and S. Yajima. Design verification of asynchronous sequential circuits using symbolic model checking. Proc. International Symposium on Logic Synthesis and Microprocessor Architecture, pp. 84-90 (1992).