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Volumn 8, Issue 4, 1997, Pages 441-447

A heuristic storage for minimizing access time of arbitrary data patterns

Author keywords

Boolean matrices; Heuristics; Memory organization; NP complete; Parallel memories; Performance evaluation; Storage schemes

Indexed keywords

BOOLEAN ALGEBRA; COST EFFECTIVENESS; DATA STORAGE EQUIPMENT; DATA TRANSFER; HEURISTIC PROGRAMMING; MATRIX ALGEBRA; NONLINEAR PROGRAMMING; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS);

EID: 0031117383     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.588625     Document Type: Article
Times cited : (4)

References (12)
  • 1
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    • Dec.
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    • (1975) IEEE Trans. Computers , vol.24 , Issue.12
    • Lawrie, D.1
  • 2
    • 0015204214 scopus 로고
    • The Organization and Use of Parallel Memories
    • Dec.
    • P. Budnik and D. Kuck, "The Organization and Use of Parallel Memories," IEEE Trans. Computers, vol. 20, no. 12, pp. 1,566-1,569, Dec. 1971.
    • (1971) IEEE Trans. Computers , vol.20 , Issue.12
    • Budnik, P.1    Kuck, D.2
  • 3
    • 0027311457 scopus 로고
    • High-Bandwidth Interleaved Memories for Vector Processors - A Simulation Study
    • Jan.
    • G.S. Sohi, "High-Bandwidth Interleaved Memories for Vector Processors - A Simulation Study," IEEE Trans. Computers, vol. 42, no. 1, pp. 34-44, Jan. 1993.
    • (1993) IEEE Trans. Computers , vol.42 , Issue.1 , pp. 34-44
    • Sohi, G.S.1
  • 5
    • 0023565195 scopus 로고
    • A Class of Boolean Linear Transformations for Conflict-Free Power-of-Two Stride Access
    • A. Norton and E. Melton, "A Class of Boolean Linear Transformations for Conflict-Free Power-of-Two Stride Access," Proc. Int'l Conf. Parallel Processing, pp. 247-254, 1987.
    • (1987) Proc. Int'l Conf. Parallel Processing , pp. 247-254
    • Norton, A.1    Melton, E.2
  • 6
    • 0017458708 scopus 로고
    • The Multidimensional Access Memory in STARAN
    • Feb.
    • K. Batcher, "The Multidimensional Access Memory in STARAN," IEEE Trans. Computers, vol. 26, no. 2, pp. 174-177, Feb. 1977.
    • (1977) IEEE Trans. Computers , vol.26 , Issue.2 , pp. 174-177
    • Batcher, K.1
  • 7
    • 33747071633 scopus 로고
    • Efficient Storage Schemes for Arbitrary Size Square Matrices in Parallel Processors with Shuffle-Exchange Networks
    • R.V. Boppana and C.S. Raghavendra, "Efficient Storage Schemes for Arbitrary Size Square Matrices in Parallel Processors with Shuffle-Exchange Networks," Proc. Int'l Conf. Parallel Processing, pp. 365-368, 1991.
    • (1991) Proc. Int'l Conf. Parallel Processing , pp. 365-368
    • Boppana, R.V.1    Raghavendra, C.S.2
  • 11
    • 0002472295 scopus 로고
    • Register Allocation and Spilling via Graph Coloring
    • G.J. Chaitan, "Register Allocation and Spilling via Graph Coloring," ACM SIGPLAN Notices, vol. 17, no. 2, pp. 201-207, 1982.
    • (1982) ACM SIGPLAN Notices , vol.17 , Issue.2 , pp. 201-207
    • Chaitan, G.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.