A DSP for DCT-based and wavelet-based video codecs for consumer applications

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 3, 1997, Pages 460-466

  Okamoto, Kiyoshi ^a,c,d,e   Jinbo, Takuya ^a,c,e,f   Araki, Toshiyuki ^a,c,e,g   Iizuka, Yasuo ^a,b,c,h,i,j   Nakajima, Hiromasa ^b   Takahata, Minoru ^b   Inoue, Hisashi ^a   Kurohmaru, Shun Ichi ^a   Yonezawa, Tomonori ^a   Aono, Kunitoshi ^a  

^a PANASONIC CORPORATION   (Japan)

^b Matsushita Electronics   (Japan)

^c Matsushita Elec Indust Co Ltd ^*

^d JOHNS HOPKINS UNIVERSITY   (United States)

^e Discovery Research Laboratories II   (Japan)

^f WASEDA UNIVERSITY   (Japan)

^g TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY   (Japan)

^h IBARAKI UNIVERSITY   (Japan)

ⁱ LSI Development Center   (Japan)

^j Institute of Image Electronics   (Japan)

more..

Author keywords

Codecs; Digital signal processing; Discrete cosine transforms; Integrated circuits; ITU T H.261; ITU T H.263; Video signal processing; Wavelet transforms

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CONSUMER ELECTRONICS; DECODING; DIGITAL SIGNAL PROCESSING; IMAGE CODING; MATHEMATICAL TRANSFORMATIONS; RANDOM ACCESS STORAGE; REAL TIME SYSTEMS; VIDEO SIGNAL PROCESSING; WAVELET TRANSFORMS;

DISCRETE COSINE TRANSFORM; QUARTER COMMON INTERMEDIATE FORMAT; VIDEO CODECS;

LSI CIRCUITS;

EID: 0031102943     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.557649     Document Type: Article

References (9)

1. "Video codec for audiovisual services at × 64 kbit/s," ITU-T Recommendation H.261, 1993.
2. "Video coding for low bitrate communication," ITU-T Draft Recommendation H.263, 1995.
3. M. Harrand et al., "A single chip videophone video encoder/decoder," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 292-293.
4. D. Brinthaupt et al., "A programmable audio/video processor for H.320, H-324, and MPEG," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 244-245.
5. K. Aono et al., "A video digital signal processor with a vector-pipeline architecture," IEEE J. Solid-State Circuits, vol. 27, pp. 1886-1894, Dec. 1992.
6. A. Peled and B. Liu, "A new hardware realization of digital filters," IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-22, pp. 456-462, Dec. 1976.
7. K. Aono et al., "A 30 ns (600MOPS) image signal processor with a reconfigurable pipeline architecture," in IEEE Proc. CICC, May 1989, pp. 24.4.1-24.4.4.
8. S. Uramoto et al., "A 100-MHz 2-D discrete cosine transform core processor," IEEE J. Solid-State Circuits, vol. 27, pp. 492-499, Apr. 1992.
9. 2 2-D DCT macrocell using senseamplifying pipeline flip-flop scheme," IEEE J. Solid-State Circuits, vol. 29, pp. 1482-1490, Dec. 1994.