Design and characterization of submicron BiCMOS compatible high-voltage NMOS and PMOS devices

IEEE Transactions on Electron Devices

Volumn 44, Issue 2, 1997, Pages 331-338

  Li, Yong Qiang ^a,c   Andre, C ^a   Salama, T ^b   Seufert, Mike ^a   Schvan, Peter ^a   King, Mike ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b Procter and Gamble Professional Oral Health   (United States)

^c Telecom Microelectronics Center   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC BREAKDOWN; ELECTRIC RESISTANCE; OPTIMIZATION; PERFORMANCE; PRODUCT DESIGN; SIMULATION;

DEVICE LAYOUT PARAMETERS; HIGH VOLTAGE BLOCKING CAPABILITY; SPECIFIC ON RESISTANCE; SUBMICRON BICMOS PROCESS; TWO DIMENSIONAL;

MOS DEVICES;

EID: 0031079244     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.557727     Document Type: Article

References (17)

1. W. G. Meyer, G. W. Dick, K. H. Olson, K. H. Lee, and J. A. Shimer, "Integrable high-voltage CMOS: Devices, process, applications," in IEDM Tech. Dig., 1985, pp. 732-735.
2. G. M. Dolny, O. H. Schade, B. Goldsmith, and L. A. Goodman, "Enhanced CMOS for analog-digital power IC applications," IEEE Trans. Electron Devices, vol. ED33, pp. 1985-1991, 1986.
3. Z. Parpia, J. Mena, and C. A. T. Salama, "A novel CMOS-compatible high-voltage transistor structure," IEEE Trans. Electron Devices, vol. ED33, pp. 1948-1952, 1986.
4. Z. Parpia, C. A. T. Salama, and R. A. Hadaway, "Modeling of CMOS-compatible high-voltage device structures," in Proc. Symp. High-Voltage and Smart Power Dev., 1987, pp. 41-50.
5. _, "Modeling and characterization of CMOS-compatible high-voltage device structures," IEEE Trans. Electron Devices, vol. ED34, pp. 2335-2343, 1987.
6. _, "A CMOS-compatible high-voltage IC process," IEEE Trans. Electron Devices, vol. 35, pp. 1687-1694, 1988.
7. M. Morikawa, I. Yoshida, H. Kojima, and Y. Kawamoto, "High-voltage MOSFET's using submicron LSI process," in Ext. Abstr. 21st Conf. Solid State Dev. and Materials, 1989, pp. 77-80.
8. T. Efland, T. Keller, S. Keller, and J. Rodriguez, "Optimized complementary 40 V power LDMOS-FET's using existing fabrication steps in submicron CMOS technology," in IEDM Tech. Dig., 1994, pp. 399-402.
9. 2 power MOSFET for intelligent driver LSI's," in Proc. 4th Int. Symp. Power Semiconductor Dev. and IC's, 1992, pp. 150-154.
10. N. Fujishima, A. Kitamura, and Y. Nagayasu, "High-performance lateral DMOSFET with oxide sidewall-spacer," in Proc. 6th Int. Symp. Power Semiconductor Dev. and IC's, 1994, pp. 349-354.
11. P. Tsui, P. Gilbert, and S. Sun, "Integration of power LDMOS into a low-voltage 0.5-μm BiCMOS technology," in IEDM Tech. Dig., 1992, pp. 27-30.
12. Y. Q. Li, C. A. T. Salama, M. Seufert, and M. King, "Submicron BiCMOS compatible high-voltage MOS transistors," in Proc. 6th Int. Symp. Power Semiconductor Dev. and IC's, 1994, pp. 355-358.
13. R. Hadaway, P. Kempf, P. Schvan, M. Rowlandson, V. Ho, J. Kolk, B. Tait, D. Sutherland, G. Jolly, and I. Emesh, "A sub-micron BiCMOS technology for telecommunications," in Proc. 21st Europ. Solid State Devices Research Conf., 1991, pp. 513-516.
14. TSUPREM4 User's Manual, Version 5. Technology Modeling Associates, Inc., 1991.
15. MEDICI User's Manual, Version 1.1.3. Technology Modeling Associates, Inc., 1992.
16. P. Tsui, P. Gilbert, and S. Sun,"A versatile half-micron complementary BiCMOS technology for micro processor-based smart power applications," IEEE Trans. Electron Devices, vol. 42, pp. 564-570, 1995.
17. Y. Q. Li, C. A. T. Salama, M. Seufert, P. Schvan, and M. King, "Integration of high-voltage NMOS devices into a submicron BiCMOS process using simple structural change," in IEDM Tech. Dig., 1994, pp. 403-406.