A method for multiple-level logic synthesis based on the simulated annealing algorithm

Microelectronics Journal

Volumn 28, Issue 2, 1997, Pages 143-150

  Lanchares, Juan ^a   Hidalgo, José Ignacio ^a   Sánchez, Juan Manuel ^b  

^a UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^b UNIVERSITY OF EXTREMADURA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; HEURISTIC METHODS; LOGIC CIRCUITS; OPTIMIZATION; SIMULATED ANNEALING; STATISTICAL METHODS;

HEURISTIC ALGORITHMS; MULTIPLE LEVEL LOGIC SYNTHESIS; SIMULATED ANNEALING ALGORITHMS;

LOGIC DESIGN;

EID: 0031078936     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0026-2692(96)00063-8     Document Type: Article

References (19)

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