Experiences with the MacTester in computer science and engineering education

IEEE Transactions on Education

Volumn 40, Issue 1, 1997, Pages 12-21

  McKenzie, Neil R ^a,b   Ebeling, Carl ^a,c   McMurchie, Larry ^a,c   Borriello, Gaetano ^a,c  

^a IEEE   (United States)

^b MITSUBISHI ELECTRIC RESEARCH LABORATORIES   (United States)

^c University of Washington   (United States)

Author keywords

Functional test and debug of ASIC's and FPGA's; Low cost hardware test environments for use in education; Mixed mode simulation of digital systems

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER DEBUGGING; COMPUTER HARDWARE; COMPUTER SCIENCE; COMPUTER SIMULATION; COMPUTER SOFTWARE; ENGINEERING EDUCATION; INTEGRATED CIRCUIT TESTING; LOGIC GATES; TESTING;

FIELD PROGRAMMABLE GATE ARRAYS; FIELD PROGRAMMABLE LOGIC DEVICE; FUNCTIONAL TESTING;

DIGITAL CIRCUITS;

EID: 0031078031     PISSN: 00189359     EISSN: None     Source Type: Journal    
DOI: 10.1109/13.554665     Document Type: Article

References (13)

1. N. R. McKenzie, L. McMurchie, and C. Ebeling, "The UW MacTester: A low-cost functional tester for interactive testing and debugging," Dept. of CSE, Univ. of Washington, Tech. Rep. UW CSE TR 92-10-08, Oct. 1992.
2. C. Ebeling and G. Borriello, "Establishing a modern digital design lab," in Proc. 4th Microelectronic Systems Education Conf., Conference Management Services, Menlo Park, CA, July 1991. Also available as Dept. of CSE, Univ. of Washington, Tech. Rep. UW CSE TR 92-08-01, Aug. 1992, ch. 4.
3. C. Ebeling and N. R. McKenzie, "MacTester: A low-cost functional tester for interactive testing and debugging," in Proc. 3rd Microelectronic Systems Education Conf., Conference Management Services, Menlo Park, CA, July 1990. Also available as Dept. of CSE, Univ. of Washington, Tech. Rep. UW CSE TR 92-08-01, Aug. 1992, ch. 3.
4. N. R. McKenzie, "The UW VLSI chip tester," Dept. of CSE, Univ. of Washington, Tech. Rep. UW CSE TR 89-12-01, Dec. 1989.
5. Xilinx Inc., The Programmable Logic Data Book, 1993, 2100 Logic Drive, San Jose, CA.
6. R. H. Katz, Contemporary Logic Design. Redwood City, CA: Benjamin/Cummings, 1994, pp. 421-426.
7. R. Bedichek, C. Ebeling, G. Winkenbach, and A. D. DeRose, "Rapid low-cost display of spline surfaces," in Advanced Research in VLSI: Proc. 1991 UCSC Conf. Cambridge, MA: MIT Press, Mar. 1991, pp. 340-355.
8. S. Hauck, G. Borriello, and C. Ebeling, "Triptych: An FPGA architecture with integrated logic and routing," in Proc. 1992 Brown/MIT Conf. on Advanced Research in VLSI and Parallel Systems. Cambridge, MA: MIT Press, Mar. 1992.
9. R. Ling and S. L. Tanimoto, "A CMOS chip for systolic cellular logic," Dept. of CSE, Univ. of Washington, Tech. Rep. UW CSE TR 90-02-05, Feb. 1990.
10. K. W. Bolding, "Chaotic routing: Design and implementation of an adaptive multicomputer network router," Ph.D. dissertation, Dept. of CSE, Univ. of Washington, July 1993.
11. R. Bedichek and C. P. Brown, "The Meerkat multicomputer," Dept. of CSE, Univ. of Washington, Tech. Rep. UW CSE TR 93-09-05, Sept. 1993.
12. A. J. Martin, S. M. Burns, T. K. Lee, D. Borkovic, and P. J. Hazewindus, "The design of an asynchronous multiprocessor," in Advanced Research in VLSI: Proc. 1989 Decennial Caltech Conf. Cambridge, MA: MIT Press, Mar. 1989, pp. 351-373.
13. M. L. Manwaring, W. I. Baker, V. D. Malbasa, and D. A. Seamans, "Universal logic implementer: A general purpose tool for a digital logic design laboratory," IEEE Trans. Educ., vol. 34, May 1991.