SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 2, 1997, Pages 232-237

  Kato, H ^a   Matsui, M ^b   Sato, K ^b   Shibata, H ^b   Hashimoto, K ^b   Ootani, T ^b   Ochii, K ^b  

^a HAKODATE NATIONAL COLLEGE OF TECHNOLOGY   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

Approving Test; Cell stabilit; Parasitic resistancey; Scaling; SRAM; VLSI

Indexed keywords

CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; DATA HANDLING; ELECTRIC RESISTANCE MEASUREMENT; INTEGRATED CIRCUIT TESTING; VLSI CIRCUITS;

STATIC RANDOM ACCESS STORAGE (SRAM);

RANDOM ACCESS STORAGE;

EID: 0031075719     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.551915     Document Type: Article

References (8)

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