Graceful degradation in algorithm-based fault tolerant multiprocessor systems

IEEE Transactions on Parallel and Distributed Systems

Volumn 8, Issue 2, 1997, Pages 137-153

  Yajnik, Shalini ^a,b   Jha, Niraj K ^a,c  

^a IEEE   (United States)

^b NOKIA RESEARCH CENTER   (United States)

^c Princeton University   (United States)

Author keywords

Algorithm based fault tolerance; Concurrent error detection; Concurrent fault location; Fault diagnosis; Graceful degradation; Transient faults

Indexed keywords

ALGORITHMS; ERROR DETECTION; FAILURE ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; GRAPH THEORY; MATHEMATICAL MODELS; PROGRAM PROCESSORS; RELIABILITY;

ALGORITHM BASED FAULT TOLERANCE; CONCURRENT ERROR DETECTION; CONCURRENT FAULT LOCATION;

MULTIPROCESSING SYSTEMS;

EID: 0031075345     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.577256     Document Type: Article

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