Decoupled sectored caches

IEEE Transactions on Computers

Volumn 46, Issue 2, 1997, Pages 210-215

  Seznec, André ^a  

^a CAMPUS DE BEAULIEU   (France)

Author keywords

Decoupled sectored caches; Second level caches; Sectored caches; Tag volume

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; MICROCOMPUTERS; MULTIPROCESSING SYSTEMS; PERFORMANCE; PROGRAM PROCESSORS;

DECOUPLED SECTORED CACHES; MICROPROCESSOR SYSTEMS; SECOND LEVEL CACHES;

BUFFER STORAGE;

EID: 0031075073     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.565601     Document Type: Article

References (8)

1. S.J. Eggers and R.H. Katz, "The Effect of Sharing on the Cache and Bus Performance" Pros. Third Conf. Architectural Support for Programming Language, and Operating Systems, Oct. 1989.
2. J.R. Goodman, "Using Cache Memory to Reduce Processor-Memory Traffic," Proc. 10th Int'l Symp. Computer Architecture (IEEE-ACM), May 1983.
3. M.D. Hill, "A Case for Direct-Mapped Caches," Computer, Dec. 1988.
4. M.D. Hill and A.J. Smith "Evaluating Associativity in CPU Caches" IEEE Trans. Computers, Dec. 1989.
5. G. Irlam "Spa," personal communication, 1992; the Spa package is available from gordoni@cs.adelaide.edu.au.
6. J. Mulder, N.T. Quach, and M.J. Flynn, "An Area Model for OnChip Memories and Its Application," IEEE J. Solid-State Circuits, pp. 96-108, Feb. 1991.
7. A. Seznec, "Interleaved Sectored Caches: Conciling Low Tag Volume and Low Miss Ratio," IRISA Research Report no. 761, Oct. 1993.
8. A. Seznec, "Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio," Pros. 21st Int'l Symp. Computer Architecture, Apr. 1994.