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Volumn 16, Issue 2, 1997, Pages 205-209

Synchronous emulation of asynchronous circuits

Author keywords

Asynchronous logic circuits; Field programmable gate arrays (fpga's), prototyping

Indexed keywords

COMPUTER SIMULATION; LOGIC GATES; SOFTWARE PROTOTYPING;

EID: 0031072205     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.573835     Document Type: Article
Times cited : (10)

References (16)
  • 1
    • 0026173694 scopus 로고
    • Computer-aided prototyping for ASIC-based systems
    • S. Walters, Computer-aided prototyping for ASIC-based systems,IEEE Design Test Computers, vol. 8, no. 2, pp. 4-10, June 1991.
    • (1991) IEEE Design Test Computers , vol.8 , Issue.2 , pp. 4-10
    • Walters, S.1
  • 2
    • 0015995299 scopus 로고
    • Toward a theory of universal speed-insensitive modules
    • R. M. Keller, Toward a theory of universal speed-insensitive modules,IEEE Trans. Comput., vol. C-23, no. 1, pp. 21-33, Jan. 1974.
    • (1974) IEEE Trans. Comput., Vol. C , vol.23 , Issue.1 , pp. 21-33
    • Keller, R.M.1
  • 6
    • 33747803307 scopus 로고    scopus 로고
    • Windchime: An FPGA-based self-timed parallel processor
    • E. Brunvand, Windchime: An FPGA-based self-timed parallel processorProc. 3rd Int. Workshop Field Programmable Logic Applications, 1993. pp. 365-376.
    • Proc. , vol.3 , pp. 365-376
    • Brunvand, E.1
  • 12
    • 0024683698 scopus 로고
    • Micropipelines
    • I. E. Sutherland, Micropipelines,Commun. ACM, vol. 32, no. 6, pp. 720-738, June 1989.
    • (1989) Commun. ACM , vol.32 , Issue.6 , pp. 720-738
    • Sutherland, I.E.1
  • 15
    • 0030356457 scopus 로고    scopus 로고
    • Retargeting a hardware compiler using protocol convenors
    • G. Brown, W. Luk, and J. O'Leary, Retargeting a hardware compiler using protocol convenors,Formal Aspects Comput., vol. 8, no. 2, pp. 209-237, 1996.
    • (1996) Formal Aspects Comput. , vol.8 , Issue.2 , pp. 209-237
    • Brown, G.1    Luk, W.2    O'Leary, J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.