Achieving high levels of instruction-level parallelism with reduced hardware complexity

HP Laboratories Technical Report

Volumn , Issue 96-120, 1997, Pages 1-85

  Schlansker, Michael S ^a   Ramakrishna Rau, B ^a   Mahlke, Scott ^a   Kathail, Vinod ^a   Johnson, Richard ^a   Anik, Sadun ^a   Abraham, Santosh G ^a  

^a Compiler and Architecture Research ^*

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER OPERATING PROCEDURES; COMPUTER OPERATING SYSTEMS; NATURAL SCIENCES COMPUTING; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS); SCHEDULING;

BRANCH PREDICTION; COMPILE TIME; DATA SPECULATION; HARDWARE COMPLEXITY; INSTRUCTION LEVEL PARALLELISM; INSTRUCTION SCHEDULING; OVERLAPPED EXECUTION; SPECULATIVE EXECUTION; SUPERSCALAR PROCESSORS;

PARALLEL PROCESSING SYSTEMS;

EID: 0031072131     PISSN: None     EISSN: None     Source Type: Report    
DOI: None     Document Type: Report

References (73)