Embedded DRAM module using a dual sense amplifier architecture in a logic process

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 64-65

  Hashimoto, Masashi ^a   Abe, Keiichiro ^a   Seshadri, Anand ^a  

^a Texas Instruments Japan Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR STORAGE;

DUAL SENSE AMPLIFIER ARRAY ARCHITECTURE (DSSA); LOGIC PROCESS COMPATIBLE DYNAMIC RANDOM ACCESS MEMORY;

RANDOM ACCESS STORAGE;

EID: 0031071383     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)