Ferroelectric field effect transistor based on epitaxial perovskite heterostructures

Science

Volumn 276, Issue 5310, 1997, Pages 238-240

  Mathews, S ^a   Ramesh, R ^a   Venkatesan, T ^a   Benedetto, J ^b  

^a UNIVERSITY OF MARYLAND   (United States)

^b U S ARMY RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARTICLE; CHEMICAL COMPOSITION; COMPUTER MEMORY; ELECTRON TRANSPORT; PRIORITY JOURNAL; SEMICONDUCTOR;

EID: 0030940516     PISSN: 00368075     EISSN: None     Source Type: Journal    
DOI: 10.1126/science.276.5310.238     Document Type: Article

References (14)

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6. D. H. Looney, U.S. Patent 2 791 758 (1957); W. L. Brown, U.S. Patent 2 791 759 (1957); I. M. Ross, U.S. Patent 2 791 760 (1957); J. A. Morton, U.S. Patent 2 791 761 (1957).
7. D. H. Looney, U.S. Patent 2 791 758 (1957); W. L. Brown, U.S. Patent 2 791 759 (1957); I. M. Ross, U.S. Patent 2 791 760 (1957); J. A. Morton, U.S. Patent 2 791 761 (1957).
8. D. H. Looney, U.S. Patent 2 791 758 (1957); W. L. Brown, U.S. Patent 2 791 759 (1957); I. M. Ross, U.S. Patent 2 791 760 (1957); J. A. Morton, U.S. Patent 2 791 761 (1957).
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12. The ferroelectric layers were patterned by in situ mechanical masking. The semiconductor channel and electrodes were patterned with photolithographic wet etch and lift-off techniques, respectively. Samples were then photolithographically patterned again and ion-milled in order to isolate individual devices. The perovskite semiconductor layer, LCMO, was between 300 to 500 Å thick. The ferroelectric layer, PZT, was between 3000 and 4000 Å in thickness. Platinum electrodes, 1000 Å in thickness, were deposited ex situ after the patterning of the other layers. Analysis by x-ray diffraction, performed before patterning and electrode deposition, indicated that no undesirable phases were formed and that both the LCMO and PZT were well-oriented with strong [001] texture. Rutherford backscattering data confirmed that the film stochiometry was consistent (within error) with that of the target materials. Transmission electron microscopy showed that the interfaces were sharp and smooth with no significant interdiffusion or formation of secondary phases. Pulsed hysteresis loops were acquired at room temperature with a Radiant Technologies RT-66A measurement system in order to determine the ferroelectric properties of the PZT layer.
13. The hysteresis loops in Figs. 1 and 3 are shifted slightly toward negative gate voltages. We attribute this shift to the fact that the top and bottom electrodes are made of different materials. Because the carrier concentration and electronic work function of the top and bottom electrodes are different, we expact this type of asymmetry in the hysteresis of the devices.
14. S.M. and R.R. would like to acknowledge the support of the U.S. Department of Army Federated Laboratories. T.V. would like to acknowledge the support of NSF grant DMR 9404579.