High-speed memory architectures for multimedia applications: Meeting the requirements of higher performance

IEEE Circuits and Devices Magazine

Volumn 13, Issue 1, 1997, Pages 8-13

  Oshima, Yoichi ^a,b,c   Sheu, Bing J ^b,d   Jen, Steve H ^b  

^a Japan Patent Office   (Japan)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^c IEEE   (Japan)

^d University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; INTERACTIVE COMPUTER SYSTEMS; PERFORMANCE; RANDOM ACCESS STORAGE; RESPONSE TIME (COMPUTER SYSTEMS); SYNCHRONIZATION; TECHNOLOGY TRANSFER; USER INTERFACES;

APPLICATION SPECIFIC MEMORY; DATA THROUGHPUT; EXTENDED DATA OUT; HIGH DENSITY STORAGE; HIGH SPEED MEMORY ARCHITECTURES; LARGE MEMORY BANDWIDTH; MULTIMEDIA APPLICATIONS;

COMPUTER ARCHITECTURE;

EID: 0030871569     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.566166     Document Type: Article

References (4)

1. Y. Takai, et al., "250M bytes/s synchronous DRAM using 3-stage-pipelined architecture," IEEE Journal of Solid-State Circuits, vol. 29, no. 4, pp. 426-431, April 1994.
2. N. Kuniyama, et al., "500 Mbytes/s data-rate 512 K bits x9 DRAM using a novel I/O interface," IEEE Symposium on VLSI Circuits Digest, pp. 66-67, Seattle, WA, May 1992.
3. K. Dosaka, et al., "A 100 MHz 4MB cache DRAM with fast copy-back scheme," IEEE Journal of Solid-State Circuits, vol. 27, no. II, pp. 1534-1539, Nov. 1992.
4. S. Gjessing. et al., "A RAM link for high speed," JEEE Spectrum, vol. 29, no. 10, pp. 52-53, Oct 1992.