Self-aligned offset gated poly-Si TFT's with a floating sub-gate

IEEE Electron Device Letters

Volumn 18, Issue 1, 1997, Pages 16-18

  Park, Cheol Min ^a   Min, Byung Hyuk ^a   Jun, Jae Hong ^a   Yoo, Juhn Suk ^a   Han, Min Koo ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC PROPERTIES; GATES (TRANSISTOR); PHOTORESISTS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES;

FLOATING SUB GATE; GATE OXIDE; IMPLANTATION MASK; PHOTORESIST REFLOW PROCESS; SELF ALIGNED OFFSET GATED POLYSILICON THIN FILM TRANSISTOR;

THIN FILM TRANSISTORS;

EID: 0030828213     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.553062     Document Type: Article

References (7)

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