Architectural support for reducing communication overhead in multiprocessor interconnection networks

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 1997, Pages 343-352

  Dao, Binh Vien ^a   Yalamanchili, Sudhakar ^a   Duato, Jose ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; DATA COMMUNICATION SYSTEMS; INTERFACES (COMPUTER); PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; TELECOMMUNICATION TRAFFIC;

COMMUNICATION LOCALITY;

INTERCONNECTION NETWORKS;

EID: 0030817442     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (24)