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Volumn , Issue , 1997, Pages 106-111
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Thermally constrained placement of smart-power IC's and multi-chip modules
a
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Author keywords
[No Author keywords available]
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Indexed keywords
DEGRADATION;
INTEGRATED CIRCUIT LAYOUT;
INTEGRATED CIRCUITS;
ITERATIVE METHODS;
MATHEMATICAL MODELS;
MATRIX ALGEBRA;
MULTICHIP MODULES;
OPTIMIZATION;
POWER ELECTRONICS;
TEMPERATURE DISTRIBUTION;
THERMAL EFFECTS;
THERMAL GRADIENTS;
COST FUNCTION;
POWER DISSIPATING COMPONENTS;
SMART POWER INTEGRATED CIRCUITS;
THERMAL MATRIX;
THERMAL PROFILES;
THERMALLY CONSTRAINED PLACEMENT;
ELECTRONICS PACKAGING;
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EID: 0030787692
PISSN: 10652221
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (12)
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References (12)
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