Symbolic fault modelling of MOS combinational circuits

Microelectronics Reliability

Volumn 37, Issue 1, 1997, Pages 137-157

  Petković, Predrag M ^a   Milovanović, Dragiša P ^a   Litovski, Vančo B ^a  

^a UNIVERSITY OF NI   (Serbia)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE; LOGIC GATES; MOS DEVICES; SEMICONDUCTOR DEVICE MODELS; TRANSISTORS;

SYMBOLIC FAULT MODELING; TRANSISTOR LOGIC CONDUCTANCE FUNCTION (TLCF);

COMBINATORIAL CIRCUITS;

EID: 0030737068     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/0026-2714(95)00245-6     Document Type: Article

References (13)

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